Advertisement
22.6.2 User Program Mode.............................................................................................. 803
22.7 Programming/Erasing Flash Memory................................................................................ 805
22.7.1 Program Mode ...................................................................................................... 806
22.7.2 Program-Verify Mode .......................................................................................... 807
22.7.3 Erase Mode ........................................................................................................... 811
22.7.4 Erase-Verify Mode................................................................................................ 811
22.8 Protection ........................................................................................................................... 813
22.8.1 Hardware Protection ............................................................................................. 813
22.8.2 Software Protection .............................................................................................. 814
22.8.3 Error Protection .................................................................................................... 815
22.9 Flash Memory Emulation in RAM .................................................................................... 817
22.10 Interrupt Handling when Programming/Erasing Flash Memory ....................................... 819
22.11 Flash Memory Programmer Mode ..................................................................................... 819
22.11.1 Socket Adapter Pin Correspondence Diagram ..................................................... 820
22.11.2 Programmer Mode Operation ............................................................................... 822
22.11.3 Memory Read Mode ............................................................................................. 823
22.11.4 Auto-Program Mode ............................................................................................. 826
22.11.5 Auto-Erase Mode.................................................................................................. 828
22.11.6 Status Read Mode ................................................................................................. 830
22.11.7 Status Polling ........................................................................................................ 831
22.11.8 Programmer Mode Transition Time ..................................................................... 831
22.11.9 Notes on Memory Programming .......................................................................... 832
22.12 Flash Memory and Power-Down States ............................................................................ 833
22.12.1 Note on Power-Down States................................................................................. 833
22.13 Flash Memory Programming and Erasing Precautions...................................................... 834
22.14 Note on Switching from F-ZTAT Version to Mask ROM Version................................... 839
Section 23 Clock Pulse Generator
23.1 Overview............................................................................................................................ 841
23.1.1 Block Diagram...................................................................................................... 841
23.1.2 Register Configuration.......................................................................................... 842
23.2 Register Descriptions ......................................................................................................... 842
23.2.1 System Clock Control Register (SCKCR)............................................................ 842
23.2.2 Low-Power Control Register (LPWRCR)............................................................ 843
23.3 Oscillator............................................................................................................................ 844
23.3.1 Connecting a Crystal Resonator............................................................................ 844
23.3.2 External Clock Input ............................................................................................. 847
23.4 PLL Circuit ........................................................................................................................ 849
23.5 Medium-Speed Clock Divider ........................................................................................... 849
23.6 Bus Master Clock Selection Circuit................................................................................... 849
23.7 Subclock Oscillator............................................................................................................ 850
23.8 Subclock Waveform Shaping Circuit ................................................................................ 851
23.9 Note on Crystal Resonator ................................................................................................. 851
................................................................................... 841
xv
Advertisement
