Advertisement
TCSR is an 8-bit readable/writable* register. Its functions include selecting the clock source to be
input to TCNT, and the timer mode.
TCSR0 (TCSR1) is initialized to H'18 (H'00) by a reset and in hardware standby mode. It is not
initialized in software standby mode.
Note: * TCSR is write-protected by a password to prevent accidental overwriting. For details see
section 15.2.5, Notes on Register Access.
Bit 7—Overflow Flag (OVF): Indicates that TCNT has overflowed from H'FF to H'00.
Bit 7
OVF
Description
0
[Clearing conditions]
•
Cleared when 0 is written to the TME bit (Only applies to WDT1)
•
Cleared by reading TCSR when OVF = 1, then writing 0 to OVF
1
[Setting condition]
When TCNT overflows (changes from H'FF to H'00)
When internal reset request generation is selected in watchdog timer mode, OVF is
cleared automatically by the internal reset.
Bit 6—Timer Mode Select (WT/IT): Selects whether the WDT is used as a watchdog timer or
interval timer. When TCNT overflows, WDT0 generates the WDTOVF signal when in watchdog
timer mode, or a WOVI interrupt request to the CPU when in interval timer mode. WDT1
generates a reset or NMI interrupt request when in watchdog timer mode, or a WOVI interrupt
request to the CPU when in interval timer mode.
WDT0 Mode Select
WDT0
WT/IT
Description
0
Interval timer mode: WDT0 requests an interval timer interrupt (WOVI)
from the CPU when the TCNT overflows.
Watchdog timer mode: WDT0 outputs a WDTOVF signal when the TCNT overflows.*
1
Note: * For details on a TCNT overflow in watchdog timer mode, see section 15.2.3, Reset
Control/Status Register (RSTCSR).
568
(Initial value)
(Initial value)
Advertisement
