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11.2.5
Timer Status Register (TSR)
Channel 0: TSR0
Channel 3: TSR3
Bit
:
Initial value :
R/W
:
Note: * Only 0 can be written, for flag clearing.
Channel 1: TSR1
Channel 2: TSR2
Channel 4: TSR4
Channel 5: TSR5
Bit
:
TCFD
Initial value :
R/W
:
Note: * Only 0 can be written, for flag clearing.
The TSR registers are 8-bit registers that indicate the status of each channel. The TPU has six TSR
registers, one for each channel. The TSR registers are initialized to H'C0 by a reset, and in
hardware standby mode.
7
6
—
—
1
1
—
—
7
6
—
TCFU
1
1
R
—
R/(W)*
5
4
—
TCFV
TGFD
0
0
—
R/(W)*
R/(W)*
5
4
TCFV
0
0
R/(W)*
3
2
TGFC
TGFB
0
0
R/(W)*
R/(W)*
3
2
—
—
TGFB
0
0
—
—
R/(W)*
1
0
TGFA
0
0
R/(W)*
1
0
TGFA
0
0
R/(W)*
435
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