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Ø
RES, MRES
Address bus
RD
HWR, LWR
D15 to D0
(1) (3) Reset exception handling vector address (when power-on reset, (1) = H'000000*,
(3) = H'000002; when manual reset, (1)= H'000004, (3)= H'000006)
(2) (4) Start address (contents of reset exception handling vector address)
(5)
Start address ((5) = (2) (4))
(6)
First program instruction
Note: * 3 program wait states are inserted.
84
*
(1)
Figure 4-2 Reset Sequence (Modes 4 and 5)
Vector
Internal
fetch
processing
*
(3)
High
(2)
(4)
Prefetch of first program
instruction
*
(5)
(6)
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