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22.5.6
Flash Memory Power Control Register (FLPWCR)
Bit:
Initial value:
R/W:
FLPWCR enables or disables a transition to the flash memory power-down mode when the LSI
switches to subactive mode.
Bit 7—Power-Down Disable (PDWND): Enables or disables a transition to the flash memory
power-down mode when the LSI switches to subactive mode.
Bit 7
PDWND
0
1
Bits 6 to 0—Reserved: These bits always read 0.
22.5.7
Serial Control Register X (SCRX)
Bit:
Initial value:
R/W:
SCRX is an 8-bit readable/writable register that controls on-chip flash memory.
SCRX is initialized to H'00 by a reset and in hardware standby mode.
Bit 7—Reserved: This bit should always be written with 0.
2
Bits 6 and 5—I
C Transfer Rate Select (IICX1, IICX0): These bits, together with bits CKS2 to
CKS0 in ICMR, select the transfer rate in master mode. For details of the transfer rate, see section
2
18.2.4, I
C Bus Mode Register (ICMR).
2
Bit 4—I
C Master Enable (IICE): Controls access to the I
control registers (ICCR, ICSR, ICDR/SARX, ICMR/SAR). For details of the control, see section
18.2.7, Serial Control Register X (SCRX).
7
6
PDWND
—
0
0
R/W
R
Description
Transition to flash memory power-down mode enabled
Transition to flash memory power-down mode disabled
7
6
—
IICX1
0
0
R/W
R/W
5
4
—
—
0
0
R
R
5
4
IICX0
IICE
FLSHE
0
0
R/W
R/W
2
C bus interface data registers and
3
2
—
—
0
0
R
R
3
2
—
0
0
R/W
R/W
1
0
—
—
0
0
R
R
(Initial value)
1
0
—
—
0
0
R/W
R/W
797
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