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14.2.2
PWM D/A Data Registers A and B (DADRA and DADRB)
15
Bit (CPU)
13
Bit (Data)
DA13
DADRA
1
Initial value :
R/W
R/W
:
DADRB
DA13
Initial value :
1
R/W
:
R/W
There are two 16-bit readable/writable PWM D/A data registers: DADRA and DADRB. DADRA
corresponds to PWM D/A channel A, and DADRB to PWM D/A channel B. The CPU can read
and write the PWM D/A data register values, but since DADRA and DADRB are 16-bit registers,
data transfers between them and the CPU are performed using a temporary register (TEMP). See
section 14.3, Bus Master Interface, for details.
The least significant (CPU) bit of DADRA is not used and is always read as 1.
DADR is initialized to H'FFFF by a reset, and in the standby modes, watch mode, subactive mode,
subsleep mode, and module stop mode.
Bits 15 to 3—PWM D/A Data 13 to 0 (DA13 to DA0): The digital value to be converted to an
analog value is set in the upper 14 bits of the PWM D/A data register.
In each base cycle, the DACNT value is continually compared with these upper 14 bits to
determine the duty cycle of the output waveform, and to decide whether to output a fine-
adjustment pulse equal in width to the resolution. To enable this operation, the data register must
be set within a range that depends on the carrier frequency select bit (CFS). If the DADR value is
outside this range, the PWM output is held constant.
A channel can be operated with 12-bit precision by keeping the two lowest data bits (DA0 and
DA1) cleared to 0 and writing the data to be converted in the upper 12 bits. The two lowest data
bits correspond to the two highest counter (DACNT) bits.
DADRH
14
13
12
11
12
11
10
9
DA12
DA11
DA10
DA9
1
1
1
1
R/W
R/W
R/W
R/W
DA12
DA11
DA10
DA9
1
1
1
1
R/W
R/W
R/W
R/W
10
9
8
7
8
7
6
5
DA8
DA7
DA6
DA5
1
1
1
1
R/W
R/W
R/W
R/W
DA8
DA7
DA6
DA5
1
1
1
1
R/W
R/W
R/W
R/W
DADRL
6
5
4
3
4
3
2
1
DA4
DA3
DA2
DA1
1
1
1
1
R/W
R/W
R/W
R/W
DA4
DA3
DA2
DA1
1
1
1
1
R/W
R/W
R/W
R/W
2
1
0
0
—
—
DA0
CFS
—
1
1
1
R/W
R/W
—
DA0
CFS
REGS
1
1
1
R/W
R/W
R/W
551
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