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Hitachi H8S/2633 Hardware Manual page 583

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15.1.2
Block Diagram
Figure 15-1 (a) and 15-1 (b) show a block diagram of the WDT.
WOVI 0
(interrupt request
signal)
WDTOVF
Internal reset signal *
Legend
: Timer control/status register
TCSR
: Timer counter
TCNT
: Reset control/status register
RSTCSR
Note: *
The type of internal reset signal depends on a register setting.
There are two alternative types of reset, namely power-on reset and manual reset.
564
Overflow
Interrupt
control
Reset
control
RSTCSR
Module bus
Figure 15-1 (a) Block Diagram of WDT0
Clock
Clock
select
TCNT
TSCR
WDT
ø/2
ø/64
ø/128
ø/512
ø/2048
ø/8192
ø/32768
ø/131072
Internal clock
sources
Bus
interface

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