Hitachi H8S/2633 Hardware Manual page 270

8.5.3 Idle Mode
Idle mode can be specified by setting the RPE bit and DTIE bit in DMACR to 1. In idle mode, one
byte or word is transferred in response to a single transfer request, and this is executed the number
of times specified in ETCR.
One address is specified by MAR, and the other by IOAR. The transfer direction can be specified
by the DTDIR bit in DMACR.
Table 8-7 summarizes register functions in idle mode.
Table 8-7 Register Functions in Idle Mode
Register
23
MAR
23 15
H'FF
IOAR
15
ETCR
Legend
MAR : Memory address register
IOAR : I/O address register
ETCR : Transfer count register
DTDIR : Data transfer direction bit
MAR specifies the start address of the transfer source or transfer destination as 24 bits. MAR is
neither incremented nor decremented each time a byte or word is transferred.
IOAR specifies the lower 16 bits of the other address. The 8 bits above IOAR have a value of
H'FF.
Function
DTDIR = 0 DTDIR = 1 Initial Setting
0
Source Destination
address address
register register
0
Destination Source
address address
register register
0
Transfer counter
Start address of
transfer destination
or transfer source
Start address of
transfer source or
transfer destination
Number of transfers Decremented every
Operation
Fixed
Fixed
transfer; transfer
ends when count
reaches H'0000
245