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Full access
Burst access
T
T
T
T
1
2
1
1
ø
Low address only changes
Address bus
CS0
AS
RD
Data bus
Read data
Read data Read data
Figure 7-32 (b) Example Burst ROM Access Timing (AST0=BRSTS1=0)
7.7.3
Wait Control
As with the basic bus interface, either program wait insertion or pin wait insertion using the WAIT
pin can be used in the initial cycle (full access) of the burst ROM interface. See Section 7.4.5,
Wait Control.
Wait states cannot be inserted in the burst cycle.
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