Table of Contents
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M
mantissa
see floating point number
memory access
via the BR register
via address in ACCU 1
memory card
memory organization
mode of operation of CPU
multiprocessor communication
application examples
assignment list
buffering data
data amount
initializing
modes
receive data
send data
sequence
test mode
multiprocessor mode
data exchange between CPUs
and CPs
data exchange with HDBs
programming
N
NAU (power failure)
nesting depth
nesting program execution levels
no operation
O
O area
see I/Os
operand areas
OR see results codes
organization block (OB)
general
organization blocks
for communication in SOFT STOP
organization blocks (OB)
as user interfaces
for processing errors
special function organization blocks
OS (overflow latching)
see results codes
OV (overflow)
see results codes
OVERALL RESET
CPU 948 Programming Guide
C79000-G8576-C848-04
P
P area
see I/Os
9-6
page area/DPR
9-22
occupied register
9-8
pages
3-10
accessing
9-4
parameters for DX 0
1-5
PARE (parity error)
6-62
PG functions
10-53
PG functions via S5 bus
10-37
PG interface module
10-17
PG screen form
10-15
for DX 0 parameter assignment
10-33
for generating DB1
10-35
PG software
10-47
PG submodule
10-40
installing
10-15
removing
10-14
PLC identification field
priority
process image
10-7
outputs (PIQ)
10-8
defining/transferring
10-9
inputs (PII)
general
inputs (PII)
outputs (PIQ)
updating
4-19, 4-28
PROCESS INTERRUPT
3-9
process interrupts
4-6
disable
3-33
enable
process interrupts via input byte IB 0
general
user interfaces
programstoring
program blocks (PB)
1-11
program execution level
general
program execution levels
2-12, 2-16
programming
general
2-20
programming language
C with S5-C compiler
2-18
GRAPH 5
2-20
SCL
6-4
STEP 5
programming language SCL
programming tools
4-14
List of Key Words
11-27
11-17
10-10
1-6, 4-5, 4-7, 4-33, 4-42, 7-10
3-72, 4-45
2-12, 2-16
4-6, 6-32
Index - 3
9-30
9-29
1-8
5-28
11-4
7-14
1-18
12-5
12-6
8-42
1-5
6-20
1-5
1-11
1-11
1-11
4-29
4-29
3-72
4-41
4-41
3-10
4-4
1-15
1-18
1-18
1-18
1-18
1-18
1-18
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