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Operations with the Base Address Register (BR Register)
Sequence
Result
Error reaction
9 - 26
The location used is the low byte of the word addressed by the BR
register plus the constant. If the content of the low byte is '0', the TSG
operation enters the slot ID in the location.
Testing (reading) and possible occupation of the location (writing)
form a program unit that cannot be interrupted.
You can evaluate the result of the test using condition codes CC 0 and
CC 1:
CC 1
CC 0
Description
0
0
The "occupied" register contains '0'. The CPU
enters its own slot ID.
1
0
The slot ID of the CPU is already entered
in the "occupied" register.
0
1
The "occupied" register contains a
different slot ID.
Note
All CPUs that require synchronized access to a common global
memory area must use the TSG operation.
The absolute address must be between F 0000H and F FFFFH. If the
absolute addresses are not in the range shown, the CPU detects a
transfer error (TRAF) and calls OB 32. If OB 32 is not loaded, the
CPU changes to the STOP mode with the error code TRAF (ISTACK).
CPU 948 Programming Guide
C79000-G8576-C848-04
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