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Programming Examples in the STL, LAD and CSF Methods of Representation
Timer operations (continued)
ON-delay timer
Logical/circuit diagram
I 3.5
I 3.5
R
S
9s 0
T 3
Q4.2
The timer is started during the first scan if the RLO
is "1". An RLO of "1" during subsequent scans does
not affect the timer.
When the RLO is "0", the timer is reset (cleared).
The scan AT or OT produces the signal "1" when the
timer has elapsed and the RLO is still applied to the
input.
KT 9.2:
The timer is loaded with the specified value (9). The
number to the right of the decimal point indicates
the time base:
0 = 0.1sec
2 = 10 sec
1 = 0.1 sec
3 = 10 sec
3 - 42
Statement
list
A
I
3.5
L
KT
9.2
SD
T
3
AN
I
3.5
R
T
3
A
T
3
=
Q
4.2
T 3
Q4.2
STEP 5 representation
Ladder
diagram
T3
I 3.5
T
O
KT9.2
TW
BI
DE
Q4.2
I 3.5
R
Q
I 3.5
Q4.2
T
CPU 948 Programming Guide
Control system
flowchart
T3
I 3.5
T
O
KT9.2
TV
BI
DE
Q4.2
R
Q
=
C79000-G8576-C848-04
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