Structure Of The Memory Area - Siemens CPU 948 Programming Manual

Structure of the Memory Area

8.1 Structure of the Memory Area
Table 8-1 Structure of the memory area
User memory for: OBs, FBs, FXs, PBs, SBs, DBs, DXs
Serial communications interface area:
System area:
Timers:
Counters:
Flags:
Flags:
Process image (PI) inputs/
outputs:
Peripheral area,
divided into:
1)
S flags occupy 8 bits in the 16-bit area. The high byte is undefined.
8 - 4
The memory of the CPU 948 is essentially divided into the following
areas:
Memory area
RI, RJ
RS, RT
T
C
F
S
PII, PIQ
"P" peripherals
"O" peripherals
Interprocessor communication flags
Coordinator (COR) (semaphore, ...)
Dual-port RAM pages (CP, IP, COR 923C)
Distributed peripherals
Hardware registers
The next section lists the addresses of the memory areas shown.
Note
When using STEP 5, you should not access a memory register
within an operand area (e.g., flags) directly via the absolute
address of the memory register. This can result in undesirable
operating statuses. Access it only relative to the base address of its
operand area.
Direct access to the areas I, Q and F result in 'FFH' in the high
byte and the data in the low byte. For direct access to S flags, the
high byte is undefined!
Data width Location
16 bits
16 bits
CPU
16 bits
16 bits
internal
16 bits
8 bits
1)
8 bits
8 bits
On the
8 bits
8 bits S5 bus
8 bits
8 bits
8/16 bits
8 bits
8/16 bits
CPU 948 Programming Guide
C79000-G8576-C848-04