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Table 5-7 continued:
Load and transfer error (TRAF)
Collision of timed interrupts:
a) queue overflow (control bit WEFES)
b) timed interrupt clock was masked (ignored) for too long
(WEFEH)
Error during STEP 5 operation "G DB/GX DX"
(control bit FEDBX)
Error in self-test (refer to Section 5.7)
1)
The CPU changes to the STOP mode only if the addressing error is not disabled by the STEP 5 operation "IAE".
Examples of reactions to
organization blocks which are
not loaded
a) No reaction; cyclic program processing is not interrupted.
If a timeout error occurs and neither OB 23 nor OB 25 is loaded, cyclic program processing is not
interrupted according to the table above. The CPU does not react.
If you want the CPU to go into the STOP mode when a timeout error occurs, you must enter a stop
statement (STP for STOP at cycle end) in the appropriate organization block (e.g. OB 23 with QVZ) and
terminate it with the block end statement 'BE'.
Example of OB 23:
:
:
:STP
:BE
b) Reaction : the CPU changes to the STOP mode.
The CPU changes to the STOP mode immediately when a corresponding error (e.g. cycle or
load/transfer error) occurs - if you did not load the appropriate organization blocks.
If, as an exception, you do not want one of these errors to interrupt cyclic program processing
(e.g. while putting the system into operation), a block end statement in the appropriate
organization block is sufficient.
Example of OB 25:
:
:
:BE
CPU 948 Programming Guide
C79000-G8576-C848-04
Cause of error
QVZ has occurred
Cyclic processing is aborted
CPU changes to the stop mode
ADF occurred
Cyclic processing is continued, no CPU STOP
Error Handling Using Organization Blocks
Organization
Reaction of CPU
block called
OB 32
OB 33
OB 34
OB 36
if OB is not
programmed
STOP
STOP
none
STOP
none
5 - 21
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