Control Bits - Siemens CPU 948 Programming Manual

Control Bits and Interrupt Stack
5.4.1

Control Bits

C O N T R O L
SYSTEM DESCRIPTION:
STOP CAUSE:
START-UP IDs:
ERROR IDs:
Fig. 5-1 Example of the first screen form page "OUTPUT ISTACK": control bits
5 - 10
When you display the ISTACK on your programmer, the status of the
control bits is indicated on the first page (see Fig. 5-1).
Note
The ISTACK screen form shown in Fig. 5-1 reflects the PG
software STEP 5/ST, Version 6.3 or STEP 5/MT Version 6.0 with
the "Delta diskette CPU 948". In older versions of the PG
software, the abbreviations of the control bits may be different.
The meaning of the control bits, however, is as described in the
following tables.
B I T S
GEP
E0VH
X X
BSTG
TEST
PGSTP HALT
UPROG USYS
NEUDF WIEDF
X
AWEG
ANEG
X
QVZIN PARIN
FE2S SRAMF
FDX0 FMODE
You can output the control bits in every mode. They mark the current or
previous status of the CPU and provide information on specific features
of the CPU and your STEP 5 program.
The control bits listed under ERROR IDS mark errors that can occur
in the RESTART (e.g., during an initial cold restart) and RUN (e.g.,
during time-controlled program processing) modes. If several errors
occur, all errors are displayed in the control bits.
MEHRP SYNCR
BATT EINP
BEFG
MCG
X
STP STS STOPS BEARBE
UANL SYSFHL
AFEL
WIEZU URLER
URLDF NEUZU
MSEG
BSTKF BSTEF UMCG
UAFEHL KDB1 KDX0
WEFES DB0UN
FEDBX QVZNIO
CPU 948 Programming Guide
C79000-G8576-C848-04
MODUN
FDB1