Table of Contents
Advertisement
Transferring Memory Blocks
Sequence
TNW, TXB and TXW
operations
Special features
Interruptions
by POWER DOWN
Interruptions by QVZ
9 - 20
Addresses
Table 9-5 continued:
E 8000H to E 9FFFH
E B000H to E FBFFH
E A000H to E AFFFH
E FC00H to E FFFFH
F 0000H to F FFFFH
(Refer also to Chapter 8)
The field transfer is made in descending order, i.e. it begins with the
highest address of the source area (= end address) and ends with the
lowest.
The operations TNW, TXB and TXW are long-running STEP 5
operations which can only be interrupted by POWER DOWN and
QVZ.
If one of the operations is interrupted by a power failure (NAU)
followed by a warm restart, the operation does not resume at the point
at which it was interrupted but from the beginning again.
If a timeout (QVZ) occurs during the transfer, the operation is
interrupted and the appropriate error OB called.
The error address is the address at which an error occurred (refer to
Section 5.6.3).
Memory area
System RAM:
System data, 16 bits
System data (RI/RS, timers, counters etc.),
16 bits
S flags, 8 bits, low byte in 16-bit word
(High byte not defined)
Flags, process image, 8 bits
(High byte = FFH)
I/Os, 8/16 bits
CPU 948 Programming Guide
C79000-G8576-C848-04
Advertisement
Table of Contents
