Access To External Address Space - Hitachi F-ZTAT H8/3039 Series Hardware Manual

ø
Address bus
AS , RD WR ,
D to D
7 0
Figure 2-18 Pin States during Access to On-Chip Supporting Modules

2.9.4 Access to External Address Space

The external address space is divided into eight areas (areas 0 to 7). Bus-controller settings
determine whether each area accessed in two or three states. For details see section 6, Bus
Controller.
54
T
1
High
High impedance
T
2
Address
T
3