Hitachi F-ZTAT H8/3039 Series Hardware Manual page 103

5.2.3 IRQ Status Register (ISR)
ISR is an 8-bit readable/writable register that indicates the status of IRQ
interrupt requests.
Bit 7
—
Initial value 0
Read/Write —
Reserved bits
Note: * Only 0 can be written, to clear flags.
ISR is initialized to H'00 by a reset and in hardware standby mode.
Bits 7, 6, 3 and 2—Reserved: These bits cannot be modified and are always read as 0.
Bits 5, 4, 1 and 0—IRQ
These bits indicate the status of IRQ
Bits 5, 4, 1, and 0
IRQ5F, IRQ4F,
IRQ1F, and IRQ0F
0
1
Note: n = 5, 4, 1 and 0
6 5 4
— IRQ5F IRQ4F
0 0 0
— R/(W)* R/(W) *
IRQ to IRQ flags
5 4
These bits indicate IRQ
interrupt request status
, IRQ , IRQ and IRQ
5 4 1
to IRQ
4
Description
[Clearing conditions]
0 is written in IRQnF after reading the IRQnF flag when IRQnF = 1.
IRQnSC = 0, IRQn input is high, and interrupt exception handling is
carried out.
IRQnSC = 1 and IRQn interrupt exception handling is carried out.
[Setting conditions]
IRQnSC = 0 and IRQn input is low.
IRQnSC = 1 and IRQn input changes from high to low.
3 2
— —
0 0
— —
Reserved bits
and IRQ
5 4
Flags (IRQ5F, IRQ4F, IRQ1F, and IRQ0F):
0
interrupt requests.
0
, IRQ , IRQ , and IRQ
0 1 4
1 0
IRQ1F IRQ0F
0 0
R/(W) * R/(W) *
IRQ , IRQ flags
0
1
These bits indicates IRQ
interrupt request status
(Initial value)
5
and IRQ
1 0
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