Hitachi F-ZTAT H8/3039 Series Hardware Manual page 4

2.9.1 Overview .............................................................................................................. 52
2.9.2 On-Chip Memory Access Timing ........................................................................ 52
2.9.3 On-Chip Supporting Module Access Timing....................................................... 53
2.9.4 Access to External Address Space ....................................................................... 54
Section 3 MCU Operating Modes
3.1 Overview............................................................................................................................ 55
3.1.1 Operating Mode Selection.................................................................................... 55
3.1.2 Register Configuration .........................................................................................
3.2 Mode Control Register (MDCR) .......................................................................................
3.3 System Control Register (SYSCR).................................................................................... 58
3.4 Operating Mode Descriptions............................................................................................ 60
3.4.1 Mode 1.................................................................................................................. 60
3.4.2 Mode 3.................................................................................................................. 60
3.4.3 Mode 5.................................................................................................................. 60
3.4.4 Mode 6.................................................................................................................. 60
3.4.5 Mode 7.................................................................................................................. 60
3.5 Pin Functions in Each Operating Mode.............................................................................
3.6 Memory Map in Each Operating Mode.............................................................................
3.7 Restrictions on Use of Mode 6 .......................................................................................... 70
Section 4 Exception Handling
4.1 Overview............................................................................................................................ 73
4.1.1 Exception Handling Types and Priority ............................................................... 73
4.1.2 Exception Handling Operation ............................................................................. 73
4.1.3 Exception Vector Table........................................................................................ 74
4.2 Reset .................................................................................................................................. 76
4.2.1 Overview .............................................................................................................. 76
4.2.2 Reset Sequence..................................................................................................... 76
4.2.3 Interrupts after Reset ............................................................................................ 78
4.3 Interrupts............................................................................................................................ 78
4.4 Trap Instruction .................................................................................................................
4.5 Stack Status after Exception Handling .............................................................................. 79
4.6 Notes on Stack Usage........................................................................................................ 80
Section 5 Interrupt Controller
5.1 Overview............................................................................................................................ 81
5.1.1 Features ................................................................................................................ 81
5.1.2 Block Diagram...................................................................................................... 82
5.1.3 Pin Configuration .................................................................................................
5.1.4 Register Configuration .........................................................................................
5.2 Register Descriptions.........................................................................................................
5.2.1 System Control Register (SYSCR) ...................................................................... 84
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