Hitachi SH7709S Manuals

Manuals and User Guides for Hitachi SH7709S. We have 1 Hitachi SH7709S manual available for free PDF download: Hardware Manual

Hitachi SH7709S Hardware Manual (788 pages)

SuperH RISC engine

Brand: Hitachi | Category: Computer Hardware | Size: 2.64 MB

Table of Contents
6
Overview and Pin Functions

20
- SH7709S Features
  20
- Block Diagram
  25
- Pin Description
  26
  - Pin Assignment
    26
  - Pin Function
    28
Cpu

38
- Register Configuration
  38
  - Privileged Mode and Banks
    38
  - General Registers
    41
  - System Registers
    42
  - Control Registers
    42
- Data Formats
  44
  - Data Format in Registers
    44
  - Data Format in Memory
    44
- Instruction Features
  45
  - Execution Environment
    45
  - Addressing Modes
    47
  - Instruction Formats
    51
- Instruction Set
  54
  - Instruction Set Classified by Function
    54
  - Instruction Code Map
    70
- Processor States and Processor Modes
  73
  - Processor States
    73
  - Processor Modes
    74
Memory Management Unit (MMU)

76
- Overview
  76
  - Features
    76
  - Role of MMU
    76
  - Sh7709S Mmu
    79
  - Register Configuration
    84
- Register Description
  84
- TLB Functions
  86
  - Configuration of the TLB
    86
  - TLB Indexing
    88
  - TLB Address Comparison
    89
  - Page Management Information
    91
- MMU Functions
  92
  - MMU Hardware Management
    92
  - MMU Software Management
    92
  - MMU Instruction (LDTLB)
    93
  - Avoiding Synonym Problems
    95
- MMU Exceptions
  97
- Configuration of Memory-Mapped TLB
  103
  - Data Array
    104
  - Usage Examples
    106
- Usage Note
  106
Exception Handling

108
- Overview
  108
  - Features
    108
  - Register Configuration
    108
- Exception Handling Function
  108
  - Exception Handling Flow
    108
  - Exception Vector Addresses
    109
  - Acceptance of Exceptions
    111
  - Exception Codes
    113
  - Exception Request Masks
    114
  - Returning from Exception Handling
    114
- Register Descriptions
  115
- Exception Handling Operation
  116
  - Reset
    116
  - Interrupts
    116
  - General Exceptions
    117
- Individual Exception Operations
  117
  - Resets
    117
  - General Exceptions
    118
  - Interrupts
    121
- Cautions
  123
Cache

126
- Overview
  126
  - Features
    126
  - Cache Structure
    126
  - Register Configuration
    128
- Register Description
  128
  - Cache Control Register (CCR)
    128
  - Cache Control Register 2 (CCR2)
    129
- Cache Operation
  132
  - Searching the Cache
    132
  - Read Access
    134
  - Prefetch Operation
    134
  - Write Access
    134
  - Write-Back Buffer
    134
  - Coherency of Cache and External Memory
    135
- Memory-Mapped Cache
  135
  - Address Array
    135
  - Data Array
    136
  - Examples of Usage
    138
Interrupt Controller (INTC)

140
- Overview
  140
  - Features
    140
  - Block Diagram
    141
  - Pin Configuration
    142
  - Register Configuration
    143
- Interrupt Sources
  144
  - NMI Interrupt
    144
  - IRQ Interrupts
    144
  - IRL Interrupts
    145
  - PINT Interrupts
    147
  - On-Chip Peripheral Module Interrupts
    147
  - Interrupt Exception Handling and Priority
    148
- INTC Registers
  154
- INTC Operation
  166
  - Interrupt Sequence
    166
  - Multiple Interrupts
    168
- Interrupt Response Time
  168
User Break Controller

172
- Overview
  172
  - Features
    172
  - Block Diagram
    173
  - Register Configuration
    174
- Register Descriptions
  175
  - Break Address Register a (BARA)
    175
  - Break Address Mask Register a (BAMRA)
    176
  - Break Bus Cycle Register a (BBRA)
    177
  - Break Address Register B (BARB)
    179
  - Break Address Mask Register B (BAMRB)
    180
  - Break Data Register B (BDRB)
    181
  - Break Data Mask Register B (BDMRB)
    182
  - Break Bus Cycle Register B (BBRB)
    183
  - Break Control Register (BRCR)
    185
  - Execution Times Break Register (BETR)
    189
  - Branch Source Register (BRSR)
    190
  - Branch Destination Register (BRDR)
    191
  - Break ASID Register a (BASRA)
    192
  - Break ASID Register B (BASRB)
    192
- Operation Description
  193
  - Flow of the User Break Operation
    193
  - Break on Instruction Fetch Cycle
    194
  - Break by Data Access Cycle
    194
  - Sequential Break
    195
  - Value of Saved Program Counter
    195
  - PC Trace
    196
  - Usage Examples
    197
  - Notes
    201
Power-Down Modes

204
- Overview
  204
  - Pin Configuration
    206
  - Register Configuration
    206
- Register Descriptions
  206
  - Standby Control Register (STBCR)
    206
  - Standby Control Register 2 (STBCR2)
    208
- Sleep Mode
  210
  - Transition to Sleep Mode
    210
  - Canceling Sleep Mode
    210
- Standby Mode
  211
  - Transition to Standby Mode
    211
  - Canceling Standby Mode
    212
  - Clock Pause Function
    213
- Module Standby Function
  214
  - Transition to Module Standby Function
    214
  - Clearing Module Standby Function
    214
- Timing of STATUS Pin Changes
  215
  - Timing for Resets
    215
  - Timing for Canceling Standby
    217
  - Timing for Canceling Sleep Mode
    219
- Hardware Standby Mode
  222
On-Chip Oscillation Circuits

226
- Overview
  226
  - Features
    226
- Overview of CPG
  227
  - CPG Block Diagram
    227
  - CPG Pin Configuration
    229
  - CPG Register Configuration
    229
- Clock Operating Modes
  230
- Register Descriptions
  234
  - Frequency Control Register (FRQCR)
    234
- Changing the Frequency
  236
  - Changing the Multiplication Rate
    236
  - Changing the Division Ratio
    236
- Overview of WDT
  237
  - Block Diagram of WDT
    237
  - Register Configuration
    237
- Wdtregisters
  238
- Using the WDT
  241
  - Canceling Standby
    241
  - Changing the Frequency
    241
  - Using Watchdog Timer Mode
    242
  - Using Interval Timer Mode
    242
- Notes on Board Design
  243
Section 10 Bus State Controller (BSC)

246
- Overview
  246
  - Features
    246
  - Block Diagram
    248
  - 10.1.3 Pin Configuration
    249
  - Register Configuration
    251
  - Area Overview
    252
  - PCMCIA Support
    255
- BSC Registers
  258
- BSC Operation
  283
  - Endian/Access Size and Data Alignment
    283
  - Description of Areas
    288
  - Basic Interface
    291
  - Synchronous DRAM Interface
    299
  - Burst ROM Interface
    328
  - PCMCIA Interface
    331
  - Waits between Access Cycles
    343
  - Bus Arbitration
    344
  - Bus Pull-Up
    345
  - 10.3.10 MCS[0] to MCS[7] Pin Control
    347
Section 11 Direct Memory Access Controller (DMAC)

350
- Overview
  350
  - Features
    350
  - Block Diagram
    352
  - Pin Configuration
    353
  - Register Configuration
    354
- Register Descriptions
  356
- Operation
  368
  - DMA Transfer Flow
    368
  - DMA Transfer Requests
    370
  - Channel Priority
    372
  - DMA Transfer Types
    375
  - Number of Bus Cycle States and DREQ Pin Sampling Timing
    386
  - Source Address Reload Function
    395
  - DMA Transfer Ending Conditions
    397
- Compare Match Timer (CMT)
  399
  - Overview
    399
  - Register Descriptions
    400
  - Operation
    403
  - Compare Match
    404
- Examples of Use
  406
- Usage Notes
  410
Section 12 Timer (TMU)

412
- Overview
  412
  - Features
    412
  - Block Diagram
    413
  - Pin Configuration
    414
  - Register Configuration
    414
- TMU Registers
  415
  - Timer Output Control Register (TOCR)
    415
  - Timer Start Register (TSTR)
    415
  - Timer Control Registers (TCR)
    416
  - Timer Constant Registers (TCOR)
    420
  - Timer Counters (TCNT)
    420
  - Input Capture Register (TCPR2)
    422
- TMU Operation
  423
  - General Operation
    423
  - Input Capture Function
    426
- Interrupts
  427
  - Status Flag Setting Timing
    427
  - Status Flag Clearing Timing
    428
  - Interrupt Sources and Priorities
    428
- Usage Notes
  429
  - Writing to Registers
    429
  - Reading Registers
    429
Section 13 Realtime Clock (RTC)

430
- Overview
  430
  - Features
    430
  - Block Diagram
    431
  - Pin Configuration
    432
  - RTC Register Configuration
    433
- RTC Registers
  434
  - 64-Hz Counter (R64CNT)
    434
  - Second Counter (RSECCNT)
    434
  - Minute Counter (RMINCNT)
    435
  - Hour Counter (RHRCNT)
    435
  - Day of Week Counter (RWKCNT)
    436
  - Date Counter (RDAYCNT)
    437
  - Month Counter (RMONCNT)
    437
  - Year Counter (RYRCNT)
    438
  - Second Alarm Register (RSECAR)
    438
  - Minute Alarm Register (RMINAR)
    439
  - Hour Alarm Register (RHRAR)
    439
  - Day of Week Alarm Register (RWKAR)
    440
  - Date Alarm Register (RDAYAR)
    441
  - Month Alarm Register (RMONAR)
    441
  - RTC Control Register 1 (RCR1)
    442
  - RTC Control Register 2 (RCR2)
    443
- RTC Operation
  445
  - Initial Settings of Registers after Power-On
    445
  - Setting the Time
    445
  - Reading the Time
    446
  - Alarm Function
    447
  - Crystal Oscillator Circuit
    448
- Usage Notes
  449
  - Register Writing During RTC Count
    449
  - Use of Realtime Clock (RTC) Periodic Interrupts
    449
Section 14 Serial Communication Interface (SCI)

450
- Overview
  450
  - Features
    450
  - Block Diagram
    451
  - Pin Configuration
    454
  - Register Configuration
    455
- Register Descriptions
  455
- Operation
  477
  - Overview
    477
  - Operation in Asynchronous Mode
    479
  - Multiprocessor Communication
    489
  - Synchronous Operation
    498
- SCI Interrupts
  508
- Usage Notes
  509
Section 15 Smart Card Interface

512
- Overview
  512
  - Features
    512
  - Block Diagram
    513
  - Pin Configuration
    514
  - Smart Card Interface Registers
    514
- Register Descriptions
  515
  - Smart Card Mode Register (SCSCMR)
    515
  - Serial Status Register (SCSSR)
    516
- Operation
  517
  - Overview
    517
  - Pin Connections
    518
  - Data Format
    519
  - Register Settings
    520
  - Clock
    521
  - Data Transmission and Reception
    524
- Usage Notes
  530
  - Receive Data Timing and Receive Margin in Asynchronous Mode
    530
  - Retransmission (Receive and Transmit Modes)
    532
Section 16 Serial Communication Interface with FIFO (SCIF)

534
- Overview
  534
  - Features
    534
  - Block Diagram
    535
  - Pin Configuration
    538
  - Register Configuration
    539
- Register Descriptions
  540
  - Receive Shift Register (SCRSR)
    540
  - Receive FIFO Data Register (SCFRDR)
    540
  - Transmit Shift Register (SCTSR)
    540
  - Transmit FIFO Data Register (SCFTDR)
    541
  - Serial Mode Register (SCSMR)
    541
  - Serial Control Register (SCSCR)
    543
  - Serial Status Register (SCSSR)
    545
  - Bit Rate Register (SCBRR)
    550
  - FIFO Control Register (SCFCR)
    558
  - FIFO Data Count Register (SCFDR)
    560
- Operation
  561
  - Overview
    561
  - Serial Operation
    562
- SCIF Interrupts
  574
- Usage Notes
  575
Section 17 Irda

578
- Overview
  578
  - Features
    578
  - Block Diagram
    579
  - Pin Configuration
    582
  - Register Configuration
    583
- Register Description
  584
  - Serial Mode Register (SCSMR)
    584
- Operation Description
  586
  - Overview
    586
  - Transmitting
    586
  - Receiving
    587
Section 18 Pin Function Controller

588
- Overview
  588
- Register Configuration
  592
- Register Descriptions
  593
  - Port a Control Register (PACR)
    593
  - Port B Control Register (PBCR)
    594
  - Port C Control Register (PCCR)
    595
  - Port D Control Register (PDCR)
    596
  - Port E Control Register (PECR)
    597
  - Port F Control Register (PFCR)
    598
  - Port G Control Register
    599
  - Port H Control Register (PHCR)
    600
  - Port J Control Register (PJCR)
    602
  - Port K Control Register (PKCR)
    603
  - Port L Control Register (PLCR)
    604
  - SC Port Control Register (SCPCR)
    605
Section 19 I/O Ports

610
- Overview
  610
- Port a
  610
  - Register Description
    610
  - Port a Data Register (PADR)
    611
- Port B
  612
  - Register Description
    612
  - Port B Data Register (PBDR)
    613
- Port C
  614
  - Register Description
    614
  - Port C Data Register (PCDR)
    615
- Port D
  616
  - Register Description
    616
  - Port D Data Register (PDDR)
    617
- Port E
  618
  - Register Description
    618
  - Port E Data Register (PEDR)
    619
- Port F
  620
  - Register Description
    620
  - Port F Data Register (PFDR)
    621
- Port G
  622
  - Register Description
    622
  - Port G Data Register
    623
- Port H
  624
  - Register Description
    624
  - Port H Data Register (PHDR)
    625
- Port J
  626
  - 19.10.1 Register Description
    626
  - Port J Data Register (PJDR)
    627
- Port K
  628
  - 19.11.1 Register Description
    628
  - Port K Data Register (PKDR)
    629
- Port L
  630
  - 19.12.1 Register Description
    630
  - Port L Data Register (PLDR)
    631
- SC Port
  632
  - 19.13.1 Register Description
    632
  - Port SC Data Register (SCPDR)
    633
Section 20 A/D Converter

636
- Overview
  636
  - Features
    636
  - Block Diagram
    637
  - Input Pins
    638
  - Register Configuration
    639
- Register Descriptions
  640
- Bus Master Interface
  645
- Operation
  646
  - Single Mode (MULTI = 0)
    646
  - Multi Mode (MULTI = 1, SCN = 0)
    648
  - Scan Mode (MULTI = 1, SCN = 1)
    650
  - Input Sampling and A/D Conversion Time
    652
  - External Trigger Input Timing
    653
- Interrupts
  654
- Definitions of A/D Conversion Accuracy
  654
- Usage Notes
  655
  - Setting Analog Input Voltage
    655
  - Processing of Analog Input Pins
    655
  - Access Size and Read Data
    656
Section 21 D/A Converter

658
- Overview
  658
  - Features
    658
  - Block Diagram
    658
  - I/O Pins
    659
  - Register Configuration
    659
- Register Descriptions
  660
  - D/A Data Registers 0 and 1 (DADR0/1)
    660
  - D/A Control Register (DACR)
    660
- Operation
  662
Section 22 Hitachi User Debugging Interface (H-UDI)

664
- Overview
  664
- Hitachi User Debugging Interface (H-UDI)
  664
  - Pin Descriptions
    664
  - Block Diagram
    665
- Register Descriptions
  665
  - Bypass Register SDBPR
    666
  - Instruction Register (SDIR)
    666
  - Boundary Scan Register (SDBSR)
    667
- H-UDI Operation
  674
  - TAP Controller
    674
  - Reset Configuration
    675
  - H-UDI Reset
    675
  - H-UDI Interrupt
    676
  - Bypass
    676
  - Using H-UDI to Recover from Sleep Mode
    676
- Boundary Scan
  676
  - Supported Instructions
    676
  - Points for Attention
    678
- Usage Notes
  678
- Advanced User Debugger (AUD)
  678
Section 23 Electrical Characteristics

680
- Absolute Maximum Ratings
  680
- DC Characteristics
  682
- AC Characteristics
  686
  - Clock Timing
    687
  - Control Signal Timing
    698
  - AC Bus Timing
    701
  - Basic Timing
    703
  - Burst ROM Timing
    706
  - Synchronous DRAM Timing
    709
  - PCMCIA Timing
    727
  - Peripheral Module Signal Timing
    734
  - H-UDI-Related Pin Timing
    737
  - 23.3.10 AC Characteristics Measurement Conditions
    739
  - 23.3.11 Delay Time Variation Due to Load Capacitance
    740
- A/D Converter Characteristics
  741
- D/A Converter Characteristics
  741
Appendix A Pin Functions

742
- Pin States
  742
- Pin Specifications
  746
- Treatment of Unused Pins
  751
- Pin States in Access to each Address Space
  752
Appendix B Memory-Mapped Control Registers

766
- Register Address Map
  766
- Register Bits
  772
Appendix C Product Lineup

784
Appendix D Package Dimensions

785

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Hitachi SH7709S Manuals

Hitachi SH7709S Hardware Manual (788 pages)

Table of Contents

Overview and Pin Functions

Cpu

Memory Management Unit (MMU)

Exception Handling

Cache

Interrupt Controller (INTC)

User Break Controller

Power-Down Modes

On-Chip Oscillation Circuits

Section 10 Bus State Controller (BSC)

Section 11 Direct Memory Access Controller (DMAC)

Section 12 Timer (TMU)

Section 13 Realtime Clock (RTC)

Section 14 Serial Communication Interface (SCI)

Section 15 Smart Card Interface

Section 16 Serial Communication Interface with FIFO (SCIF)

Section 17 Irda

Section 18 Pin Function Controller

Section 19 I/O Ports

Section 20 A/D Converter

Section 21 D/A Converter

Section 22 Hitachi User Debugging Interface (H-UDI)

Section 23 Electrical Characteristics

Appendix A Pin Functions

Appendix B Memory-Mapped Control Registers

Appendix C Product Lineup

Appendix D Package Dimensions

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