Next Data Register A (Ndra) - Hitachi F-ZTAT H8/3039 Series Hardware Manual

9.2.5 Next Data Register A (NDRA)

NDRA is an 8-bit readable/writable register that stores the next output data for TPC output groups
1 and 0 (pins TP to TP
7
TPCR occurs, NDRA contents are transferred to the corresponding bits in PADR. The address of
NDRA differs depending on whether TPC output groups 0 and 1 have the same output trigger or
different output triggers.
NDRA is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Same Trigger for TPC Output Groups 0 and 1: If TPC output groups 0 and 1 are triggered by
the same compare match event, the NDRA address is H'FFA5. The upper 4 bits belong to group 1
and the lower 4 bits to group 0. Address H'FFA7 consists entirely of reserved bits that cannot be
modified and always read 1.
Address H'FFA5
Bit
NDR7
Initial value
Read/Write R/W
Address H'FFA7
Bit
Initial value
Read/Write
). During TPC output, when an ITU compare match event specified in
0
7 6
NDR6 NDR5
0 0
R/W R/W
Next data 7 to 4
These bits store the next output
data for TPC output group 1
7 6
— —
1 1
— —
5 4
NDR4 NDR3
0 0
R/W R/W
5 4
— —
1 1
— —
Reserved bits
3 2
NDR2 NDR1
0 0
R/W R/W
Next data 3 to 0
These bits store the next output
data for TPC output group 0
3 2
— —
1 1
— —
1 0
NDR0
0 0
R/W
1 0
— —
1 1
— —
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