Timer Output Master Enable Register (Toer) - Hitachi F-ZTAT H8/3039 Series Hardware Manual

Bit 1—Buffer Mode B3 (BFB3): Selects whether GRB3 operates normally in channel 3, or
whether GRB3 is buffered by BRB3.
Bit 1
BFB3 Description
0 GRB3 operates normally
1 GRB3 is buffered by BRB3
Bit 0—Buffer Mode A3 (BFA3): Selects whether GRA3 operates normally in channel 3, or
whether GRA3 is buffered by BRA3.
Bit 0
BFA3 Description
0 GRA3 operates normally
1 GRA3 is buffered by BRA3

8.2.5 Timer Output Master Enable Register (TOER)

TOER is an 8-bit readable/writable register that enables or disables output settings for channels 3
and 4.
Bit
Initial value
Read/Write
Reserved bits
TOER is initialized to H'FF by a reset and in standby mode.
206
7 6
— — EXB4
1 1
— — R/W
Master enable TOCXA
These bits enable or disable output
settings for pins TOCXA
5 4 3
EXA4 EB3
1 1 1
R/W R/W
, TOCXB
4
and TOCXB
4
Master enable TIOCA
These bits enable or disable output settings for pins
TIOCA , TIOCB
3 3
2 1
EB4 EA4
1 1
R/W R/W
4
4
, TIOCB , TIOCA
3 3
, TIOCA , and TIOCB
4
(Initial value)
(Initial value)
0
EA3
1
R/W
, TIOCB
4 4
4