Hitachi F-ZTAT H8/3039 Series Hardware Manual page 328

Bit 7—Watchdog Timer Reset (WRST): During watchdog timer operation, this bit indicates that
TCNT has overflowed and generated a reset signal. This reset signal resets the entire chip
internally. If bit RSTOE is set to 1, this reset signal is also output (low) at the RESO pin*
initialize external system devices.
Bit 7
WRST Description
0 [Clearing condition]
(1) Cleared to 0 by reset signal input at RES pin
(2) Cleared by reading WRST when WRST = 1, then writing 0 in
WERST
1 [Setting condition]
Set when TCNT overflow generates a reset signal during
watchdog timer operation
Bit 6—Reset Output Enable (RSTOE): Enables or disables external output at the RESO pin*
the reset signal generated if TCNT overflows during watchdog timer operation.
Bit 6
RSTOE Description
0 Reset signal is not output externally
1 Reset signal is output externally*
Bits 5 to 0—Reserved: These bits cannot be modified and are always read as 1.
Notes: 1. Masked ROM version. Dedicated FWE input pin for F-ZTAT version.
2. Masked ROM version. Do not set to 1 with the F-ZTAT version.
318
2
1
to
(Initial value)
1
of
(Initial value)