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16.3 Duty Adjustment Circuit
When the oscillator frequency is 5 MHz or higher, the duty adjustment circuit adjusts the duty
cycle of the clock signal from the oscillator to generate the system clock (ø).
16.4 Prescalers
The prescalers divide the system clock (ø) to generate internal clocks (ø/2 to ø/4096).
16.5 Frequency Divider
The frequency divider divides the duty-adjusted clock signal to generate the system clock (ø). The
frequency division ratio can be changed dynamically by modifying the value in DIVCR, as
described below. Power consumption in the chip is reduced in almost direct proportion to the
frequency division ratio. The system clock generated by the frequency divider can be output at the
ø pin.
16.5.1 Register Configuration
Table 16-5 summarizes the frequency division register.
Table 16-5 Frequency Division Register
Address*
H'FF5D
Note: * The lower 16 bits of the address are shown.
498
Name
Division control register
Abbreviation
R/W
DIVCR
R/W
Initial Value
H'FC
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