Hitachi F-ZTAT H8/3039 Series Hardware Manual page 497

φ
t
OSC1
V
CC
FWE
MD to MD
2 0
RES
SWE bit
Mode switching *
Flash memory access disabled time
(x: Wait time after SWE setting)
Flash memory reprogammable period
(Flash memory program execution and data read, other than verify, are disabled.)
Notes: 1.
In transition to the boot mode and transition from the boot mode to another mode,
mode switching via RES input is necessary.
During this switching period (period during which a low level is input to the RES pin),
the state of the address dual port and bus control output signals (AS,RD,WR) changes.
Therefore, do not use these pins as output signals during this switching period.
2.
When making a transition from the boot mode to another mode, the mode programming
setup time t
3.
See 18.2.5 Flash Memory Characteristics.
(Example: Boot mode → User mode ↔ User program mode)
488
Programming and
Wait time: x erase possible
t
MDS
t
MDS
SWE set
1 Boot mode
Mode
switching *
3
*
relative to the RES clear timing is necessary.
MDS
Figure 15-27 Mode Transition Timing
Programming
and
erase
Wait time: x possible
min 0µs
2
*
t
MDS
t
RESW
SWE clear
User User program mode
1
mode
Wait Programming and
time: x
erase possible
User
mode
Programming
and
Wait
erase
time: x
possible
User
program
mode