Hitachi H8/3032 Series Manuals

Manuals and User Guides for Hitachi H8/3032 Series. We have 1 Hitachi H8/3032 Series manual available for free PDF download: Hardware Manual

Hitachi H8/3032 Series Hardware Manual (572 pages)

Brand: Hitachi | Category: Computer Hardware | Size: 2.54 MB

Table of Contents
5
Overview
16
Block Diagram
20
Pin Description
21
Pin Arrangement
21
Pin Functions
22
Pin Functions
25
Cpu
30
Overview
30
Features
30
Differences from H8/300 CPU
31
CPU Operating Modes
32
Address Space
33
Register Configuration
34
Overview
34
General Registers
35
Control Registers
36
Initial CPU Register Values
37
Data Formats
38
General Register Data Formats
38
Memory Data Formats
39
Instruction Set
41
Instruction Set Overview
41
Instructions and Addressing Modes
42
Tables of Instructions Classified by Function
43
Basic Instruction Formats
53
Notes on Use of Bit Manipulation Instructions
54
Addressing Modes and Effective Address Calculation
54
Addressing Modes
54
Effective Address Calculation
57
Processing States
61
Overview
61
Program Execution State
62
Exception-Handling State
62
Exception-Handling Sequences
64
Reset State
65
Power-Down State
65
Basic Operational Timing
66
Overview
66
On-Chip Memory Access Timing
66
On-Chip Supporting Module Access Timing
68
Access to External Address Space
69
MCU Operating Modes
70
Overview
70
Operating Mode Selection
70
Register Configuration
71
Mode Control Register (MDCR)
72
System Control Register (SYSCR)
73
Operating Mode Descriptions
75
Mode 1
75
Mode 2
75
Mode 3
75
Pin Functions in each Operating Mode
76
Memory Map in each Operating Mode
76
Exception Handling
80
Overview
80
Exception Handling Types and Priority
80
Exception Handling Operation
80
Exception Vector Table
81
Reset
82
Overview
82
Reset Sequence
82
Interrupts after Reset
84
Trap Instruction
86
Stack Status after Exception Handling
87
Notes on Stack Usage
88
Interrupt Controller
90
Overview
90
Features
90
Block Diagram
91
Pin Configuration
92
Register Configuration
92
Register Descriptions
93
System Control Register (SYSCR)
93
Interrupt Priority Registers a and B (IPRA, IPRB)
94
IRQ Status Register (ISR)
100
IRQ Enable Register (IER)
101
IRQ Sense Control Register (ISCR)
102
Interrupt Sources
103
External Interrupts
103
Internal Interrupts
104
Interrupt Vector Table
104
Interrupt Operation
107
Interrupt Handling Process
107
Interrupt Sequence
112
Interrupt Response Time
113
Usage Notes
114
Contention between Interrupt and Interrupt-Disabling Instruction
114
Instructions that Inhibit Interrupts
115
Interrupts During EEPMOV Instruction Execution
115
Bus Controller
116
Overview
116
Features
116
Block Diagram
117
Input/Output Pins
118
Register Configuration
118
Register Descriptions
119
Access State Control Register (ASTCR)
119
Wait Control Register (WCR)
120
Wait State Controller Enable Register (WCER)
121
Operation
122
Area Division
122
Bus Control Signal Timing
124
Wait Modes
126
Interconnections with Memory (Example)
132
Usage Notes
133
Register Write Timing
133
I/O Ports
134
Overview
134
Port 1
137
Overview
137
Register Descriptions
138
Pin Functions in each Mode
139
Port 2
141
Overview
141
Register Descriptions
142
Pin Functions in each Mode
143
Input Pull-Up Transistors
145
Port 3
146
Overview
146
Register Descriptions
146
Pin Functions in each Mode
148
Port 5
149
Overview
149
Register Descriptions
149
Pin Functions in each Mode
152
Input Pull-Up Transistors
153
Port 6
154
Overview
154
Register Descriptions
154
Pin Functions in each Mode
156
Port 7
159
Overview
159
Register Description
160
Port 8
161
Overview
161
Register Descriptions
162
Pin Functions
163
Port 9
165
Overview
165
Register Descriptions
165
Pin Functions
167
Port a
168
Overview
168
Register Descriptions
169
Pin Functions
171
Port B
176
Overview
176
Register Descriptions
176
Pin Functions
178
16-Bit Integrated Timer Unit (ITU)
184
Overview
184
Features
184
Block Diagrams
187
Input/Output Pins
192
Register Configuration
193
Register Descriptions
196
Timer Start Register (TSTR)
196
Timer Synchro Register (TSNC)
197
Timer Mode Register (TMDR)
199
Timer Function Control Register (TFCR)
202
Timer Output Master Enable Register (TOER)
204
Timer Output Control Register (TOCR)
207
Timer Counters (TCNT)
208
General Registers (GRA, GRB)
209
Buffer Registers (BRA, BRB)
210
Timer Control Registers (TCR)
211
Timer I/O Control Register (TIOR)
213
Timer Status Register (TSR)
215
Timer Interrupt Enable Register (TIER)
218
CPU Interface
220
16-Bit Accessible Registers
220
8-Bit Accessible Registers
222
Operation
224
Overview
224
Basic Functions
225
Synchronization
235
PWM Mode
237
Reset-Synchronized PWM Mode
241
Complementary PWM Mode
244
Phase Counting Mode
254
Buffering
256
ITU Output Timing
263
Interrupts
265
Setting of Status Flags
265
Clearing of Status Flags
267
Interrupt Sources
268
Usage Notes
269
Programmable Timing Pattern Controller
284
Overview
284
Features
284
Block Diagram
285
TPC Pins
286
Registers
287
Register Descriptions
288
Port a Data Direction Register (PADDR)
288
Port a Data Register (PADR)
288
Port B Data Direction Register (PBDDR)
289
Port B Data Register (PBDR)
289
Next Data Register a (NDRA)
290
Next Data Register B (NDRB)
292
Next Data Enable Register a (NDERA)
294
Next Data Enable Register B (NDERB)
295
TPC Output Control Register (TPCR)
296
TPC Output Mode Register (TPMR)
299
Operation
301
Overview
301
Output Timing
302
Normal TPC Output
303
Non-Overlapping TPC Output
305
TPC Output Triggering by Input Capture
307
Usage Notes
308
Operation of TPC Output Pins
308
Note on Non-Overlapping Output
308
Watchdog Timer
310
Overview
310
Features
310
Block Diagram
311
Pin Configuration
311
Register Configuration
312
Register Descriptions
313
Timer Counter (TCNT)
313
Timer Control/Status Register (TCSR)
314
Reset Control/Status Register (RSTCSR)
316
Notes on Register Access
318
Operation
320
Watchdog Timer Operation
320
Interval Timer Operation
321
Timing of Setting of Overflow Flag (OVF)
322
Timing of Setting of Watchdog Timer Reset Bit (WRST)
323
Interrupts
324
Usage Notes
324
Serial Communication Interface
326
Overview
326
Features
326
Block Diagram
328
Input/Output Pins
329
Register Configuration
329
Register Descriptions
330
Receive Shift Register (RSR)
330
Receive Data Register (RDR)
330
Transmit Shift Register (TSR)
331
Transmit Data Register (TDR)
331
Serial Mode Register (SMR)
332
Serial Control Register (SCR)
336
Serial Status Register (SSR)
340
Bit Rate Register (BRR)
344
Operation
353
Overview
353
Operation in Asynchronous Mode
355
Multiprocessor Communication
364
Synchronous Operation
371
SCI Interrupts
380
Usage Notes
381
A/D Converter
386
Overview
386
Features
386
Block Diagram
387
Input Pins
388
Register Configuration
389
Register Descriptions
390
A/D Data Registers a to D (ADDRA to ADDRD)
390
A/D Control/Status Register (ADCSR)
391
A/D Control Register (ADCR)
394
CPU Interface
395
Operation
396
Single Mode (SCAN = 0)
396
Scan Mode (SCAN = 1)
398
Input Sampling and A/D Conversion Time
400
External Trigger Input Timing
401
Interrupts
402
Usage Notes
402
Ram
404
Overview
404
Block Diagram
404
Register Configuration
405
System Control Register (SYSCR)
406
Operation
407
Mode 1
407
Modes 2 and 3
407
Rom
408
Overview
408
Block Diagram
408
PROM Mode
409
PROM Mode Setting
409
Socket Adapter and Memory Map
409
Programming
412
Programming and Verification
412
Programming Precautions
417
Reliability of Programmed Data
418
Clock Pulse Generator
420
Overview
420
Block Diagram
420
Oscillator Circuit
421
Connecting a Crystal Resonator
421
External Clock Input
423
Duty Adjustment Circuit
425
Prescalers
425
Power-Down State
426
Overview
426
Register Configuration
427
System Control Register (SYSCR)
427
Sleep Mode
429
Transition to Sleep Mode
429
Exit from Sleep Mode
429
Software Standby Mode
430
Transition to Software Standby Mode
430
Exit from Software Standby Mode
430
Selection of Waiting Time for Exit from Software Standby Mode
431
Sample Application of Software Standby Mode
432
Note
432
Hardware Standby Mode
433
Transition to Hardware Standby Mode
433
Exit from Hardware Standby Mode
433
Timing for Hardware Standby Mode
433
Electrical Characteristics
434
Absolute Maximum Ratings
434
Electrical Characteristics
435
DC Characteristics
435
AC Characteristics
445
A/D Conversion Characteristics
452
Operational Timing
453
Bus Timing
453
Control Signal Timing
457
Clock Timing
459
TPC and I/O Port Timing
459
ITU Timing
460
SCI Input/Output Timing
461
Appendix A Instruction Set
462
Instruction List
462
Operating Code Maps
477
Number of States Required for Execution
480
Appendix B Register Field
489
Register Addresses and Bit Names
489
Register Descriptions
497
Appendix C I/O Port Block Diagrams
547
Port 1 Block Diagram
547
Port 2 Block Diagram
548
Port 3 Block Diagram
549
Port 5 Block Diagram
550
Port 6 Block Diagram
551
Port 7 Block Diagram
553
Port 8 Block Diagram
554
Port 9 Block Diagram
555
Port a Block Diagram
558
Port B Block Diagram
561
Appendix D Pin States
566
Port States in each Mode
566
Pin States at Reset
567
Appendix E Timing of Transition to and Recovery from Hardware Standby Mode
571
Appendix F Package Dimensions
572

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Hitachi H8/3032 Series Hardware Manual (572 pages)

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