System Clock Output Disabling Function - Hitachi F-ZTAT H8/3039 Series Hardware Manual

17.7 System Clock Output Disabling Function

Output of the system clock (ø) can be controlled by the PSTOP bit in MSTCR. When the PSTOP
bit is set to 1, output of the system clock halts and the ø pin is placed in the high-impedance state.
Figure 17-3 shows the timing of the stopping and starting of system clock output. When the
PSTOP bit is cleared to 0, output of the system clock is enabled. Table 17-4 indicates the state of
the ø pin in various operating states.
MSTCR write cycle
ø pin
Figure 17-3 Starting and Stopping of System Clock Output
Table 17-4 ø Pin State in Various Operating States
Operating State
Hardware standby
Software standby
Sleep mode
Normal operation
(PSTOP = 1)
T1 T2 T3
PSTOP = 0
High impedance
Always high
System clock output
System clock output
High impedance
MSTCR write cycle
(PSTOP = 0)
T1 T2 T3
PSTOP = 1
High impedance
High impedance
High impedance
High impedance
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