Timer Status Register (Tsr) - Hitachi F-ZTAT H8/3039 Series Hardware Manual

8.2.12 Timer Status Register (TSR)

TSR is an 8-bit register. The ITU has five TSRs, one in each channel.
Channel Abbreviation
0 TSR0
1 TSR1
2 TSR2
3 TSR3
4 TSR4
Bit
Initial value
Read/Write
Note: * Only 0 can be written to clear the flag.
Each TSR is an 8-bit readable/writable register containing flags that indicate TCNT overflow or
underflow and GRA or GRB compare match or input capture. These flags are interrupt sources
and generate CPU interrupts if enabled by corresponding bits in the timer interrupt enable register
(TIER).
TSR is initialized to H'F8 by a reset and in standby mode.
218
Function
Indicates input capture, compare match, and overflow status
7 6
— —
1 1
— —
Reserved bits
5 4
— —
1 1
— —
Overflow flag
Status flag indicating
overflow or underflow
Input capture/compare match flag B
Status flag indicating GRB compare
match or input capture
Input capture/compare match flag A
Status flag indicating GRA compare
match or input capture
3 2
— OVF IMFB
1 0
R/(W)
— R/(W) *
1 0
IMFA
0 0
R/(W)
* *