Hitachi F-ZTAT H8/3039 Series Hardware Manual page 510

Table 17-1 Power-Down State and Module Standby Function
Entering
Mode Conditions Clock CPU
Sleep SLEEP instruc- Active Halted
mode tion executed
while SSBY = 0
in SYSCR
Software SLEEP instruc- Halted Halted
standby tion executed
mode while SSBY = 1
in SYSCR
Hardware Low input at Halted Halted
standby STBY pin
mode
Module Corresponding Active Active
standby bit set to 1 in
function
MSTCR
Notes: 1. State in which the corresponding MSTCR bit was set to 1. For details see section 17.2.2, Module Standby Control Register (MSTCR).
2. The RAME bit must be cleared to 0 in SYSCR before the transition from the program execution state to hardware standby mode.
3. When a MSTCR bit is set to 1, the registers of the corresponding on-chip supporting module are initialized. To restart the module, first
clear the MSTCR bit to 0, then set up the module registers again.
Legend
SYSCR: System control register
SSBY: Software standby bit
MSTCR: Module standby control register
State
CPU
Registers ITU SCI0 SCI1
Held Active Active Active
Held Halted Halted Halted
and and and
reset reset reset
Undeter Halted Halted Halted
mined and and and
reset reset reset
— Halted *1 Halted *1 Halted
and and and
reset reset reset
Supporting
Modules
A/D RAM
Active Active Held
Halted Halted Held
and and
reset reset
Halted Halted Held *2
and and
reset reset
—
*1 Halted *1 Active
and
reset
φclock Exiting
I/O
output Ports
Methods
φoutput
Held • Interrupt
• RES
• STBY
High Held • NMI
output
• IRQ to IRQ
0
• RES
• STBY
High High • STBY
impedance impedance
• RES
High —
• STBY
impedance *1
• RES
• Clear MSTCR
bit to 0
1
*3