A.3 Number of States Required for Execution
The tables in this section can be used to calculate the number of states required for instruction
execution by the H8/300H CPU. Table A-3 indicates the number of states required per cycle
according to the bus size. Table A-4 indicates the number of instruction fetch, data read/write, and
other cycles occurring in each instruction. The number of states required for execution of an
instruction can be calculated from these two tables as follows:
Number of states = I × S
Examples of Calculation of Number of States Required for Execution
Examples: Advanced mode, stack located in external address space, on-chip supporting modules
accessed with 8-bit bus width, external devices accessed in three states with one wait state and
16-bit bus width.
BSET #0, @FFFFC7:8
From table A-3, S
From table A-4, I = L = 2 and J = K = M = N = 0
Number of states = 2 × 4 + 2 × 3 = 14
JSR @@30
From table A-3, S
From table A-4, I = J = K = 2 and L = M = N = 0
Number of states = 2 × 4 + 2 × 4 + 2 × 4 = 24
+ J × S
+ K × S
+ L × S
I
J
K
= 4 and S
= 3
I
L
= S
= S
= 4
I
J
K
+ M × S
+ N × S
L
M
N
579