External Trigger Input Timing - Hitachi F-ZTAT H8/3039 Series Hardware Manual

Table 13-4 A/D Conversion Time (Single Mode)
Synchronization delay
Input sampling time
A/D conversion time
Note: Values in the table are numbers of states.

13.4.4 External Trigger Input Timing

A/D conversion can be externally triggered. When the TRGE bit is set to 1 in ADCR, external
trigger input is enabled at the ADTRG pin. A high-to-low transition at the ADTRG pin sets the
ADST bit to 1 in ADCSR, starting A/D conversion. Other operations, in both single and scan
modes, are the same as if the ADST bit had been set to 1 by software. Figure 13-6 shows the
timing.
ø
ADTRG
Internal trigger
signal
ADST
426
CKS = 0
Symbol Min
t 10
D
t —
SPL
t 259
CONV
Figure 13-6 External Trigger Input Timing
Typ Max
— 17
63 —
— 266
A/D conversion
CKS = 1
Min Typ
6 —
— 31
131 —
Max
9
—
134