Signal Transmission Between The Qd73A1 And Others - Mitsubishi Electric MELSEC Q Series User Manual

1.2

Signal Transmission Between the QD73A1 and Others

The following figure shows signal transmission between the QD73A1 and a CPU module, and a drive unit.
CPU module
PLC READY signal
Y2D
QD73A1 READY signal
X11
OPR request signal
X12
OPR start signal
Y20
OPR start complete signal
X20
OPR complete signal
X13
Positioning start signal
Y21 to Y23
Positioning start complete signal
X21 to X23
BUSY signal
X14
Positioning complete signal
X15
Speed-position switching enable signal
Y2C
JOG start signal
Y24, Y25
Speed-position mode restart signal
Y26
Stop signal
Y27
Error detection signal
X18
Error reset signal
Y28
Overflow signal
X19
Overflow reset signal
Y29
Underflow signal
X1A
Underflow reset signal
Y2A
In-position signal
X16
Excessive error signal
X17
Near-point dog signal
X1C
External stop signal
X1D
Upper limit signal/Lower limit signal
X1E, X1F
Servo READY signal
X1B
WDT error, H/W error signal
X10
Synchronization flag
X24
Zero/gain adjustment data
writing request signal
Y1A
Zero/gain adjustment data
writing complete flag
X2A
Zero/gain adjustment change request signal
Y1B
Zero/gain adjustment change complete flag
X2B
Set value change request signal
Y1C
Set value change complete flag
X2C
Operating status of the speed-position
control switch mode
X2D
Data writing/reading
QD73A1
External
interface
Interface with
the CPU
module
CHAPTER 1 OVERVIEW
Stop signal (STOP)
Near-point dog signal (DOG)
Upper limit signal (FLS)
Lower limit signal (RLS)
Speed-position switching command signal
(CHANGE)
Phase-Z pulse (Zero signal)
Phase-A pulse
Phase-B pulse
Servo READY signal (READY)
Servo ON signal (SVON)
Analog voltage
1
External
control
signals
PLG
Drive unit
19