Response Delay Time - Mitsubishi Electric MELSEC iQ-R AnyWireASLINK User Manual

Master module
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Response delay time

The following shows the response delay time of input and output.
Input response delay time
The figure below shows the time from a signal input to the slave module to turning on or off of a device of the CPU module.
The input response delay time is the total of  to  in the following figure.
(1)
(2)
(3)
(1) Slave module
(2) AnyWireASLINK
(3) CPU module
No.
Description
Input response time on the slave module
Processing time on the slave module
Transmission time
Processing time on the RJ51AW12AL
Processing time on the programmable
controller
APPX
120
Appendix 4 Processing Time
Ò
Ó
Ô
Required time
Refer to the manual for the slave module connected to the system or the device connected to the
slave module.
Approx. 0.2ms (Differs depending on the slave module.)
• Bit data: Bit transmission cycle time  2
• Word data: Word transmission cycle time
The transmission cycle time varies depending on the specified number of bit data points and the
specified number of word data points. ( Page 111 Transmission cycle time)
0.6ms
• Bit data: Sequence scan time  2
• Word data: Sequence scan time  Set value of the number of word data cycles
Õ
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