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SMR0—Serial Mode Register 0
SMR1—Serial Mode Register 1
SMR2—Serial Mode Register 2
SMR3—Serial Mode Register 3
SMR4—Serial Mode Register 4
Bit
Initial value
R/W
Communication mode
0 Asynchronous mode
1 Clocked synchronous mode
:
7
6
C/A
CHR
:
0
0
:
R/W
R/W
R/W
Stop bit length
Parity mode
0 Even parity*
1 Odd parity*
Notes: 1. When even parity is set, parity bit addition is performed in transmission
so that the total number of 1 bits in the transmit character plus the parity
bit is even.
In reception, a check is performed to see if the total number of 1 bits in
the receive character plus the parity bit is even.
2. When odd parity is set, parity bit addition is performed in transmission
so that the total number of 1 bits in the transmit character plus the parity
bit is odd.
In reception, a check is performed to see if the total number of 1 bits in
the receive character plus the parity bit is odd.
Parity enable
0 Parity bit addition and checking disabled
1 Parity bit addition and checking enabled*
Note: * When the PE bit is set to 1, the parity (even or odd) specified by the O/E bit is
added to transmit data before transmission. In reception, the parity bit is checked
for the parity (even or odd) specified by the O/E bit.
Character length
0 8-bit data
1 7-bit data*
Note: * When 7-bit data is selected, the MSB (bit 7) of TDR is not transmitted, and
it is not possible to choose between LSB-first or MSB-first transfer.
H'FF78
H'FF80
H'FF88
H'FDD0
H'FDD8
5
4
3
PE
O/E
STOP
0
0
0
R/W
R/W
Clock select 1 and 0
CKS1
CKS0 Description
0
0
1
1
0
1
Multiprocessor mode
0
Multiprocessor function disabled
1
Multiprocessor format selected
0 1 stop bit:
In transmission, a single 1 bit (stop bit) is added to the
end of a transmit character before it is sent.
1 2 stop bits: In transmission, two 1 bits (stop bits) are added to the
end of a transmit character before it is sent.
1
2
2
1
0
MP
CKS1
CKS0
0
0
0
R/W
R/W
R/W
ø clock
ø/4 clock
ø/16 clock
ø/64 clock
SCI0
SCI1
SCI2
SCI3
SCI4
1015
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