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SCKCR—System Clock Control Register
Bit
:
7
PSTOP
Initial value
:
0
R/W
:
R/W
ø clock output disable
PSTOP
0
1
1024
6
5
—
—
0
0
—
—
Frequency multiplier switching mode select
0 Specified multiplier valid after transferring to software standby mode,
watch mode, and sub-active mode.
1 Specified multiplier valid immediately after setting value in STC bit.
High-speed mode,
Medium-speed mode
Sub-Sleep mode Watch mode direct transition
Sub-active mode
ø output
High level (fixed)
High level (fixed)
H'FDE6
4
3
—
STCS
0
0
—
R/W
System clock select 2 to 0
SCK2
SCK1
0
1
Sleep mode
Software standby mode
ø output
High level (fixed)
High level (fixed)
2
1
SCK2
SCK1
0
0
R/W
R/W
SCK0
0
0
Bus master set to high-speed mode.
1
Medium-speed clock: ø/2
1
0
Medium-speed clock: ø//4
1
Medium-speed clock: ø8
0
0
Medium-speed clock: ø/16
Medium-speed clock: ø/32
1
1
—
—
Hardware standby
High impedance
High impedance
System
0
SCK0
0
R/W
mode
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