Hitachi H8S/2646 Hardware Manual page 289

Port A Data Register (PADR)
Bit : 7
PA7DR
Initial value : 0
R/W : R/W
PADR is an 8-bit readable/writable register that stores output data for the port A pins (PA7 to
PA0).
PADR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in
software standby mode.
Port A Register (PORTA)
Bit : 7
PA7
Initial value : —*
R/W : R
Note: * Determined by state of pins PA7 to PA0.
PORTA is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of
output data for the port A pins (PA7 to PA0) must always be performed on PADR.
Reading a pin being used as an LCD driver returns an undefined value.
If a port A read is performed while PADDR bits are set to 1, the PADR values are read. If a port A
read is performed while PADDR bits are cleared to 0, the pin states are read.
After a reset and in hardware standby mode, PORTA contents are determined by the pin states, as
PADDR and PADR are initialized. PORTA retains its prior state in software standby mode.
6 5
PA6DR PA5DR PA4DR
0 0
R/W R/W
6 5
PA6 PA5
—* —*
R R
4 3
PA3DR PA2DR
0 0
R/W R/W R/W
4 3
PA4 PA3 PA2
—* —*
R R
2 1
PA1DR PA0DR
0 0
R/W R/W
2 1
PA1 PA0
—* —* —*
R R
0
0
0
R
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