Can Bus Interface; Usage Notes - Hitachi H8S/2646 Hardware Manual

Hitachi 16-bit single-chip microcomputer h8s/2646 series

Table of Contents

CAN Bus Interface

A bus transceiver IC is necessary to connect the H8S/2646 Series chip to a CAN bus. A Philips

PCA82C250 transceiver IC, or compatible device, is recommended. Figure 15-14 shows a sample

connection diagram.

H8S/2646 Series

Figure 15-14 High-Speed Interface Using PCA82C250

The HCAN is reset by a reset, and in hardware standby mode and software standby mode. All

the registers are initialized in a reset, but mailboxes (message control (MCx[x])/message data

(MDx[x]) are not. However, after powering on, mailboxes (message control (MCx[x])/message

data (MDx[x]) are initialized, and their values are undefined. Therefore, mailbox initialization

must always be carried out after a reset or a transition to hardware standby mode or software

standby mode. The reset interrupt flag (IRR0) is always set after a reset or recovery from

software standby mode. This bit cannot be masked by the interrupt mask register (IMR). When

a flag is not cleared and the interrupt controller enables HCAN interrupts, the HCAN interrupts

the CPU. Clear IRR0 during initialization.

2. HCAN sleep mode

The bus operation interrupt flag (IRR12) in the interrupt register (IRR) is set by bus operation

in HCAN sleep mode. Therefore, this flag is not used by the HCAN to indicate sleep mode

release. Also note that the reset status bit (GSR3) in the general status register (GSR) is set in

3. Interrupts

When the mailbox interrupt mask register (MBIMR) is set, the interrupt register (IRR8,2,1) is

not set by reception completion, transmission completion, or transmission cancellation for the

No connection