Table of Contents
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7.7
Write Data Buffer Function ............................................................................................... 178
7.8
Bus Arbitration................................................................................................................... 179
7.8.1
Overview .............................................................................................................. 179
7.8.2
Operation .............................................................................................................. 179
7.8.3
Bus Transfer Timing ............................................................................................. 179
7.9
Resets and the Bus Controller............................................................................................ 180
Section 8
Data Transfer Controller (DTC) ......................................................181
8.1
Overview............................................................................................................................ 181
8.1.1
Features ................................................................................................................. 181
8.1.2
Block Diagram...................................................................................................... 182
8.1.3
Register Configuration.......................................................................................... 183
8.2
Register Descriptions ......................................................................................................... 184
8.2.1
DTC Mode Register A (MRA) ............................................................................. 184
8.2.2
DTC Mode Register B (MRB).............................................................................. 186
8.2.3
DTC Source Address Register (SAR) .................................................................. 187
8.2.4
DTC Destination Address Register (DAR) .......................................................... 187
8.2.5
DTC Transfer Count Register A (CRA) ............................................................... 187
8.2.6
DTC Transfer Count Register B (CRB)................................................................ 188
8.2.7
DTC Enable Registers (DTCER).......................................................................... 188
8.2.8
DTC Vector Register (DTVECR) ........................................................................ 189
8.2.9
Module Stop Control Register A (MSTPCRA).................................................... 190
8.3
Operation............................................................................................................................ 192
8.3.1
Overview............................................................................................................... 192
8.3.2
Activation Sources................................................................................................ 194
8.3.3
DTC Vector Table ................................................................................................ 195
8.3.4
Location of Register Information in Address Space............................................. 199
8.3.5
Normal Mode........................................................................................................ 200
8.3.6
Repeat Mode ......................................................................................................... 201
8.3.7
Block Transfer Mode............................................................................................ 202
8.3.8
Chain Transfer ...................................................................................................... 204
8.3.9
Operation Timing.................................................................................................. 205
8.3.10 Number of DTC Execution States ........................................................................ 206
8.3.11 Procedures for Using DTC.................................................................................... 208
8.3.12 Examples of Use of the DTC................................................................................ 209
8.4
Interrupts ............................................................................................................................ 212
8.5
Usage Notes ....................................................................................................................... 212
Section 9
I/O Ports ...........................................................................................213
9.1
Overview............................................................................................................................ 213
9.2
Port 1.................................................................................................................................. 221
9.2.1
Overview............................................................................................................... 221
9.2.2
Register Configuration.......................................................................................... 222
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