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6.2.3
Break Control Register A (BCRA) ....................................................................... 132
6.2.4
Break Control Register B (BCRB) ....................................................................... 134
6.2.5
Module Stop Control Register C (MSTPCRC) .................................................... 134
6.3
Operation............................................................................................................................ 135
6.3.1
PC Break Interrupt Due to Instruction Fetch........................................................ 135
6.3.2
PC Break Interrupt Due to Data Access ............................................................... 135
6.3.3
Notes on PC Break Interrupt Handling................................................................. 136
6.3.4
Operation in Transitions to Power-Down Modes ................................................. 136
6.3.5
PC Break Operation in Continuous Data Transfer ............................................... 137
6.3.6
When Instruction Execution is Delayed by One State.......................................... 138
6.3.7
Additional Notes ................................................................................................... 139
Section 7
Bus Controller..................................................................................141
7.1
Overview............................................................................................................................ 141
7.1.1
Features ................................................................................................................. 141
7.1.2
Block Diagram...................................................................................................... 142
7.1.3
Pin Configuration.................................................................................................. 143
7.1.4
Register Configuration.......................................................................................... 143
7.2
Register Descriptions ......................................................................................................... 144
7.2.1
Bus Width Control Register (ABWCR) ............................................................... 144
7.2.2
Access State Control Register (ASTCR).............................................................. 144
7.2.3
Wait Control Registers H and L (WCRH, WCRL) .............................................. 146
7.2.4
Bus Control Register H (BCRH) .......................................................................... 150
7.2.5
Bus Control Register L (BCRL) ........................................................................... 151
7.2.6
Pin Function Control Register (PFCR) ................................................................. 152
7.3
Overview of Bus Control ................................................................................................... 154
7.3.1
Area Partitioning................................................................................................... 154
7.3.2
Bus Specifications ................................................................................................ 155
7.3.3
Memory Interfaces................................................................................................ 156
7.3.4
Interface Specifications for Each Area ................................................................. 157
7.4
Basic Bus Interface ............................................................................................................ 158
7.4.1
Overview............................................................................................................... 158
7.4.2
Data Size and Data Alignment.............................................................................. 158
7.4.3
Valid Strobes ........................................................................................................ 160
7.4.4
Basic Timing......................................................................................................... 161
7.4.5
Wait Control.......................................................................................................... 169
7.5
Burst ROM Interface.......................................................................................................... 171
7.5.1
Overview............................................................................................................... 171
7.5.2
Basic Timing......................................................................................................... 171
7.5.3
Wait Control.......................................................................................................... 173
7.6
Idle Cycle ........................................................................................................................... 174
7.6.1
Operation .............................................................................................................. 174
7.6.2
Pin States During Idle Cycles ............................................................................... 177
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