Interrupts - Hitachi H8S/2646 Hardware Manual

Hitachi 16-bit single-chip microcomputer h8s/2646 series

Table of Contents

Interrupts

Interrupt exception handling can be requested by seven external sources (NMI, IRQ5 to IRQ0) and

internal sources (43 sources in the H8S/2646, H8S/2646R, and H8S/2645, and 47 sources in the

H8S/2648, H8S/2648R, and H8S/2647) in the on-chip supporting modules. Figure 4-4 classifies

the interrupt sources and the number of interrupts of each type.

The on-chip supporting modules that can request interrupts include the watchdog timer (WDT),

16-bit timer pulse unit (TPU), serial communication interface (SCI), data transfer controller

(DTC), PC break controller (PBC), A/D converter, Hitachi controller area network (HCAN), and

motor control PWM timer. Each interrupt source has a separate vector address.

NMI is the highest-priority interrupt. Interrupts are controlled by the interrupt controller. The

interrupt controller has two interrupt control modes and can assign interrupts other than NMI to

eight priority/mask levels to enable multiplexed interrupt control.

For details of interrupts, see section 5, Interrupt Controller.

Notes: Numbers in parentheses are the numbers of interrupt sources.

* When the watchdog timer is used as an interval timer, it generates an interrupt request

at each counter overflow.

Figure 4-4 Interrupt Sources and Number of Interrupts

IRQ5 to IRQ0 (6)

SCI (8): H8S/2646, H8S/2646R, H8S/2645

SCI (12): H8S/2648, H8S/2648R, H8S/2647

A/D converter (1)