Register Descriptions; Master Control Register (Mcr) - Hitachi H8S/2646 Hardware Manual

15.2

Register Descriptions

15.2.1

Master Control Register (MCR)

The master control register (MCR) is an 8-bit readable/writable register that controls the CAN
interface.
MCR
Bit:
Initial value:
R/W:
Bit 7—HCAN Sleep Mode Release (MCR7): Enables or disables HCAN sleep mode release by
bus operation.
Bit 7: MCR7
0
1
Bit 6—Reserved: This bit always reads 0. The write value should always be 0.
Bit 5—HCAN Sleep Mode (MCR5): Enables or disables HCAN sleep mode transition.
Bit 5: MCR5
0
1
Bits 4 and 3—Reserved: These bits always read 0. The write value should always be 0.
Bit 2—Message Transmission Method (MCR2): Selects the transmission method for transmit
messages.
Bit 2: MCR2
0
1
7 6
MCR7 — MCR5
0 0
R/W R R/W
Description
HCAN sleep mode release by CAN bus operation disabled
HCAN sleep mode release by CAN bus operation enabled
Description
HCAN sleep mode released
Transition to HCAN sleep mode enabled
Description
Transmission order determined by message identifier priority (Initial value)
Transmission order determined by mailbox (buffer) number priority
(TXPR1 > TXPR15)
5 4 3
— —
0 0 0
R R
2 1
MCR2 MCR1 MCR0
0 0
R/W R/W R/W
(Initial value)
(Initial value)
0
1
535