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PWBFR2A—PWM Buffer Register 2A
PWBFR2B—PWM Buffer Register 2B
PWBFR2C—PWM Buffer Register 2C
PWBFR2D—PWM Buffer Register 2D
Bit
15
14
—
—
Initial value
1
1
Read/Write
—
—
Note: When a PWCYR2 compare match occurs, data is transferred from PWBFR2A to PWDTR2A or
PWDTR2E, from PWBFR2B to PWDTR2B or PWDTR2F, from PWBFR2C to PWDTR2C or
PWDTR2G, and from PWBFR2D to PWDTR2D or PWDTR2H.
PHDDR—Port H Data Direction Register
Bit
7
PH7DDR
Initial value
0
Read/Write
W
PJDDR—Port J Data Direction Register
Bit
7
PJ7DDR
Initial value
0
Read/Write
W
13
12
11
10
—
TDS
—
—
DT9
1
0
1
1
—
R/W
—
—
R/W
Transfer Destination Select
Selects the PWDTR2 register to which data is to be transferred
Register
TDS
PWBFR2A
0
1
PWBFR2B
0
1
PWBFR2C
0
1
PWBFR2D
0
1
6
5
PH6DDR
PH5DDR
0
0
W
W
6
5
PJ6DDR
PJ5DDR
0
0
W
W
H'FC18
H'FC1A
H'FC1C
H'FC1E
9
8
7
6
5
DT8
DT7
DT6
DT5
0
0
0
0
0
R/W
R/W
R/W
R/W
Duty
Comprise the data transferred to bits 9 to 0
in PWDTR2
Description
PWDTR2A selected
PWDTR2E selected
PWDTR2B selected
PWDTR2F selected
PWDTR2C selected
PWDTR2G selected
PWDTR2D selected
PWDTR2H selected
H'FC20
4
3
PH4DDR
PH3DDR
PH2DDR
0
0
W
W
H'FC21
4
3
PJ4DDR
PJ3DDR
0
0
W
W
4
3
2
1
DT4
DT3
DT2
DT1
0
0
0
0
R/W
R/W
R/W
R/W
2
1
PH1DDR
PH0DDR
0
0
W
W
2
1
PJ2DDR
PJ1DDR
PJ0DDR
0
0
W
W
PWM2
PWM2
PWM2
PWM2
0
DT0
0
R/W
Port
0
0
W
Port
0
0
W
953
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