Register Descriptions; System Control Register (Syscr) - Hitachi H8S/2646 Hardware Manual

5.2

Register Descriptions

5.2.1

System Control Register (SYSCR)

Bit : 7
MACS
Initial value : 0
R/W : R/W
SYSCR is an 8-bit readable/writable register that selects the interrupt control mode, and the
detected edge for NMI.
Only bits 5 to 3 are described here; for details of the other bits, see section 3.2.2, System Control
Register (SYSCR).
SYSCR is initialized to H'01 by a reset and in hardware standby mode. SYSCR is not initialized in
software standby mode.
Bits 5 and 4—Interrupt Control Mode 1 and 0 (INTM1, INTM0): These bits select one of two
interrupt control modes for the interrupt controller.
Bit 5 Bit 4
Interrupt
INTM1 INTM0 Control Mode
0 0 0
1 —
1 0 2
1 —
Bit 3—NMI Edge Select (NMIEG): Selects the input edge for the NMI pin.
Bit 3
NMIEG Description
0 Interrupt request generated at falling edge of NMI input
1 Interrupt request generated at rising edge of NMI input
104
6 5 4
— INTM1 INTM0
0 0 0
— R/W R/W
Description
Interrupts are controlled by I bit
Setting prohibited
Interrupts are controlled by bits I2 to I0, and IPR
Setting prohibited
3 2
NMIEG —
0 0
R/W R/W
1 0
— RAME
0 1
— R/W
(Initial value)
(Initial value)