External Trigger Input Timing - Hitachi H8S/2646 Hardware Manual

Table 16-4 A/D Conversion Time (Single Mode)
Item
A/D conversion start delay t
Input sampling time
A/D conversion time
Note: Values in the table are the number of states.
Table 16-5 A/D Conversion Time (Scan Mode)
CKS1 CKS0
0 0
1
1 0
1
16.4.4

External Trigger Input Timing

A/D conversion can be externally triggered. When the TRGS1 and TRGS0 bits are set to 11 in
ADCR, external trigger input is enabled at the ADTRG pin. A falling edge at the ADTRG pin sets
the ADST bit to 1 in ADCSR, starting A/D conversion. Other operations, in both single and scan
modes, are the same as if the ADST bit has been set to 1 by software. Figure 16-6 shows the
timing.
ø
ADTRG
Internal trigger signal
ADST
CKS0 = 0
Symbol Min Typ Max Min Typ Max Min Typ Max Min Typ Max
18 —
D
t — 127 —
SPL
t 55 —
CONV
Conversion Time (State)
512 (Fixed)
256 (Fixed)
128 (Fixed)
64 (Fixed)
Figure 16-6 External Trigger Input Timing
CKS1 = 0
CKS0 = 1
33 10 — 17
— 63 —
530 259 — 266 131 —
A/D conversion
CKS1 = 0
CKS0 = 0 CKS0 = 1
6 — 9 4 —
— 31 — — 15
134 67 —
5
—
68
603