Reset, Stop, Mode Select, And Interrupt Timing - Motorola DSP56367 User Manual

3.9

RESET, STOP, MODE SELECT, AND INTERRUPT TIMING

Table 3-7 Reset, Stop, Mode Select, and Interrupt Timing
No.
8
Delay from RESET assertion to all pins at reset value
9
Required RESET duration
• Power on, external clock generator,
PLL disabled
• Power on, external clock generator,
PLL enabled
• During normal operation
10 Delay from asynchronous RESET deassertion to first
external address output (internal reset deassertion)
• Minimum
• Maximum
13 Mode select setup time
14 Mode select hold time
15 Minimum edge-triggered interrupt request assertion width
16 Minimum edge-triggered interrupt request deassertion width
17 Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to
external memory access address out valid
• Caused by first interrupt instruction
fetch
• Caused by first interrupt instruction
execution
18 Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to
general-purpose transfer output valid caused by first
interrupt instruction execution
19 Delay from address output valid caused by first interrupt
instruction execute to interrupt request deassertion for level
sensitive fast interrupts
20 Delay from RD assertion to interrupt request deassertion for
level sensitive fast interrupts
MOTOROLA
Reset, Stop, Mode Select, and Interrupt Timing
Characteristics
3
4
5
1
1
DSP56367
Expression
—
50 × ET
C
1000 × ET
C
2.5 × T
C
3.25 × T
+ 2.0
C
20.25 T + 7.50
C
4.25 × T
+ 2.0
C
7.25 × T
+ 2.0
C
10 × T
+ 5.0
C
3.75 × T + WS × T
– 10.94
C C
3.25 × T + WS × T
– 10.94
C C
Specifications
Min Max Unit
— 26.0 ns
416.7 — ns
µs
8.3 —
20.8 — ns
29.1 — ns
— 176.2 ns
30.0 — ns
0.0 — ns
5.5 — ns
5.5 — ns
37.4 — ns
62.4 — ns
88.3 — ns
— Note 7 ns
— Note 7 ns
3-9