Table 5-4 Internal I/O Memory Map (Continued)
Peripheral
Address
TRIPLE TIMER
X:$FFFF8F
X:$FFFF8E
X:$FFFF8D
X:$FFFF8C
X:$FFFF8B
X:$FFFF8A
X:$FFFF89
X:$FFFF88
X:$FFFF87
X:$FFFF86
X:$FFFF85
X:$FFFF84
X:$FFFF83
X:$FFFF82
X:$FFFF81
X:$FFFF80
ESAI MUX PIN
Y:$FFFFAF
CONTROL
Y:$FFFFAE
Y:$FFFFAD
Y:$FFFFAC
Y:$FFFFAB
Y:$FFFFAA
Y:$FFFFA9
Y:$FFFFA8
Y:$FFFFA7
Y:$FFFFA6
Y:$FFFFA5
Y:$FFFFA4
Y:$FFFFA3
Y:$FFFFA2
Y:$FFFFA1
Y:$FFFFA0
PORT E
Y:$FFFF9F
Y:$FFFF9E
Y:$FFFF9D
MOTOROLA
TIMER 0 CONTROL/STATUS REGISTER (TCSR0)
TIMER 0 LOAD REGISTER (TLR0)
TIMER 0 COMPARE REGISTER (TCPR0)
TIMER 0 COUNT REGISTER (TCR0)
TIMER 1 CONTROL/STATUS REGISTER (TCSR1)
TIMER 1 LOAD REGISTER (TLR1)
TIMER 1 COMPARE REGISTER (TCPR1)
TIMER 1 COUNT REGISTER (TCR1)
TIMER 2 CONTROL/STATUS REGISTER (TCSR2)
TIMER 2 LOAD REGISTER (TLR2)
TIMER 2 COMPARE REGISTER (TCPR2)
TIMER 2 COUNT REGISTER (TCR2)
TIMER PRESCALER LOAD REGISTER (TPLR)
TIMER PRESCALER COUNT REGISTER (TPCR)
RESERVED
RESERVED
MUX PIN CONTROL REGISTER (EMUXR)
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
PORT E CONTROL REGISTER (PCRE)
PORT E DIRECTION REGISTER(PPRE)
PORT E GPIO DATA REGISTER(PDRE)
DSP56367
Memory Configuration
Internal I/O Memory Map
Register Name
5-17