Motorola DSP56367 User Manual page 103

24-bit digital signal processor
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Table 3-14 DRAM Out-of-Page and Refresh Timings, Eight Wait States
No.
Characteristics
182
WR assertion pulse width
183
WR assertion to RAS deassertion
184
WR assertion to CAS deassertion
185
Data valid to CAS assertion (write)
186
CAS assertion to data not valid
(write)
187
RAS assertion to data not valid
(write)
188
WR assertion to CAS assertion
189
CAS assertion to RAS assertion
(refresh)
190
RAS deassertion to CAS assertion
(refresh)
191
RD assertion to RAS deassertion
192
RD assertion to data valid
193
RD deassertion to data not valid
194
WR assertion to data active
195
WR deassertion to data high
impedance
Note:
1.
The number of wait states for out-of-page access is specified in the DCR.
2.
The refresh period is specified in the DCR.
3.
The asynchronous delays specified in the expressions are valid for DSP56367.
4.
RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is t
and not t
GZ
5.
Either t
RCH
MOTOROLA
4
Symbol
t
WP
t
RWL
t
CWL
t
DS
t
DH
t
DHR
t
WCS
t
CSR
t
RPC
t
ROH
t
GA
4
t
GZ
.
or t
must be satisfied for read cycles.
RRH
DSP56367
External Memory Expansion Port (Port A)
66 MHz
3
Expression
Min
8.5 × T
− 4.5
124.3
C
8.75 × T
− 4.3
128.3
C
7.75 × T
− 4.3
113.1
C
4.75 × T
− 4.0
68.0
C
3.25 × T
− 4.0
45.2
C
5.75 × T
− 4.0
83.1
C
5.5 × T
− 4.3
79.0
C
1.5 × T
− 4.0
18.7
C
1.75 × T
− 4.0
22.5
C
8.5 × T
− 4.0
124.8
C
7.5 × T
− 7.5
C
7.5 × T
− 6.5
C
0.0
0.0
0.75 × T
− 0.3
11.1
C
0.25 × T
C
Specifications
80 MHz
Max
Min
Max
101.8
105.1
92.6
55.4
36.6
67.9
64.5
14.8
17.9
102.3
106.1
87.3
0.0
9.1
3.8
3.1
3-37
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
OFF

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