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Emulator (OnCE). The DSP56300 core is described in the document DSP56300 24-Bit
Digital Signal Processor Family Manual, Motorola publication DSP56300FM/AD.
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Memory modules.
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Peripheral modules. The peripheral modules are defined in the following sections.
Memory sizes in the block diagram are defaults. Memory may be differently partitioned,
according to the memory mode of the chip. See Section 1 On-Chip Memory on page 1-10
for more details about memory size.
1.4
DSP56300 CORE FUNCTIONAL BLOCKS
The DSP56300 core provides the following functional blocks:
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Data arithmetic logic unit (Data ALU)
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Address generation unit (AGU)
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Program control unit (PCU)
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Bus interface unit (BIU)
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DMA controller (with six channels)
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Instruction cache controller
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PLL-based clock oscillator
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OnCE module
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JTAG TAP
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Memory
In addition, the DSP56367 provides a set of on-chip peripherals, described in Section 1
Peripheral Overview on page 1-11.
1.4.1
DATA ALU
The Data ALU performs all the arithmetic and logical operations on data operands in the
DSP56300 core. The components of the Data ALU are as follows:
Fully pipelined 24-bit × 24-bit parallel multiplier-accumulator (MAC)
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Bit field unit, comprising a 56-bit parallel barrel shifter (fast shift and normalization;
bit stream generation and parsing)
MOTOROLA
DSP56300 Core Functional Blocks
DSP56367
DSP56367 Overview
1-5
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