Timer Pulse (Mode 1) - Motorola DSP56367 User Manual

13.4.1.2

Timer Pulse (Mode 1)

Bit Settings
TC3 TC2 TC1
0 0 0
In this mode, the timer generates a compare interrupt when the timer count reaches a preset
value. In addition, timer 0 provides an external pulse on its TIO0 signal.
Set the TE bit to clear the counter and enable the timer. The value to which the timer is to
count is loaded into the TCPR. The counter is loaded with the TLR value when the first timer
clock signal is received. The TIO0 signal is loaded with the value of the INV bit. The timer
clock signal can be taken from either the DSP56367 clock divided by two (CLK/2) or from
the prescaler clock output. Each subsequent clock signal increments the counter.
When the counter matches the TCPR value, the TCF bit in TCSR is set and a compare
interrupt is generated if the TCIE bit is set. The polarity of the TIO0 signal is inverted for one
timer clock period.
If the TRM bit is set, the counter is loaded with the TLR value on the next timer clock and the
count is resumed. If the TRM bit is cleared, the counter continues to be incremented on each
timer clock.
This process is repeated until the TE bit is cleared (disabling the timer).
The value of the TLR sets the delay between starting the timer and the generation of the
output pulse. To generate successive output pulses with a delay of X clocks between signals,
the TLR value should be set to X/2 and the TRM bit should be set.
This process is repeated until the timer is disabled (i.e., TE is cleared).
If the counter overflows, the TOF bit is set, and if TOIE is set, an overflow interrupt is
generated.
The counter contents can be read at any time by reading the TCR.
MOTOROLA
TC0 TIO0 Clock
1 Output Internal
DSP56367
Timer/ Event Counter
Timer Modes of Operation
Mode Characteristics
# KIND
1 Timer
NAME
Pulse
13-15