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10.2.6
SERIAL TRANSMIT 5/RECEIVE 0 DATA PIN (SDO5/SDI0)
SDO5/SDI0 is used as the SDO5 signal for transmitting data from the TX5 serial transmit
shift register when programmed as transmitter pin, or as the SDI0 signal for receiving serial
data to the RX0 serial shift register when programmed as a receiver pin. SDO5/SDI0 is an
input when data is being received by the RX0 shift register. SDO5/SDI0 is an output when
data is being transmitted from the TX5 shift register. In the on-demand mode with an
internally generated bit clock, the SDO5/SDI0 pin becomes high impedance for a full clock
period after the last data bit has been transmitted, assuming another data word does not follow
immediately. If a data word follows immediately, there is no high-impedance interval.
SDO5/SDI0 may be programmed as a general-purpose I/O pin (PC6) when the ESAI SDO5
and SDI0 functions are not being used
10.2.7
RECEIVER SERIAL CLOCK (SCKR)
SCKR is a bidirectional pin providing the receivers serial bit clock for the ESAI interface. The
direction of this pin is determined by the RCKD bit in the RCCR register.The SCKR operates
as a clock input or output used by all the enabled receivers in the asynchronous mode
(SYN=0), or as serial flag 0 pin in the synchronous mode (SYN=1).
When this pin is configured as serial flag pin, its direction is determined by the RCKD bit in
the RCCR register. When configured as the output flag OF0, this pin reflects the value of the
OF0 bit in the SAICR register, and the data in the OF0 bit shows up at the pin synchronized to
the frame sync being used by the transmitter and receiver sections. When this pin is
configured as the input flag IF0, the data value at the pin is stored in the IF0 bit in the SAISR
register, synchronized by the frame sync in normal mode or the slot in network mode.
SCKR may be programmed as a general-purpose I/O pin (PC0) when the ESAI SCKR
function is not being used.
Note:
Although the external ESAI serial clock can be independent of and asynchronous
to the DSP system clock, the DSP clock frequency must be at least three times the
external ESAI serial clock frequency and each ESAI serial clock phase must
exceed the minimum of 1.5 DSP clock periods.
MOTOROLA
Enhanced Serial Audio Interface (ESAI)
DSP56367
ESAI Data and Control Pins
10-5
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